2009 Proceeding- Conference Chairs:
- Sandro Bartolini,
- Pierfrancesco Foglia,
- Roberto Giorgi,
- Cosimo Antonio Prete
MEDEA is a half day workshop that wants to be a forum for academic and industrial people to exchange ideas and experience on memory architectures for general-purpose, commercial and embedded systems. Main topics are memory architecture and memory-related performance/power issues, as well as memory management and optimization themes, considering system architecture and application domain in a joint manner. The program presents works on memory organization, performance and power in various kinds of systems (e.g. vector and heterogeneous CMP), and works on memory management on CMP architectures. We hope you enjoy the workshop.
Proceeding Downloads
Performance tuning and analysis of future vector processors based on the roofline model
- Yoshiei Sato,
- Ryuichi Nagaoka,
- Akihiro Musa,
- Ryusuke Egawa,
- Hiroyuki Takizawa,
- Koki Okabe,
- Hiroaki Kobayashi
Because of a recent steep drop in the ratio of memory bandwidth to computational performance (B/F) of vector processors, their advantage against scalar ones regarding relatively high sustained performance is decaying. To cover the insufficient B/F rate, ...
Achieving high memory performance from heterogeneous architectures with the SARC programming model
Current heterogeneous multicore architectures, including the Cell/B.E., GPUs, and future developments, like Larrabee, require enormous programming efforts to efficiently run current parallel applications, achieving high performance. In this paper, we ...
Temperature reduction analysis in Sentry Tag cache systems
Power and temperature management continue to impose challenging issues in high-performance processor design. Processor power density is growing and has made building efficient cooling systems expensive. While Dynamic Thermal Management (DTM) techniques ...
Performance balancing: software-based on-chip memory management for effective CMP executions
This paper proposes the concept of performance balancing, and reports its performance impact on a Chip multiprocessor (CMP). Integrating multiple processor cores into a single chip, or CMPs, can achieve higher peak performance by means of exploiting ...
Memory management thread for heap allocation intensive sequential applications
Dynamic memory management is one of the most ubiquitous and expensive operations in many C/C++ applications. Some C/C++ programs might spend up to one third of their execution time in dynamic memory management routines. With multicore processors as a ...
PSMalloc: content based memory management for MPI applications
Multicore processors have come to dominate the commodity market upon which many large scale systems are based. The number of cores is increasing with the speed of Moore's law and as a direct consequence, the memory available per core is decreasing, ...
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Acceptance Rates
| Year | Submitted | Accepted | Rate |
|---|---|---|---|
| MEDEA '06 | 9 | 6 | 67% |
| Overall | 9 | 6 | 67% |