skip to main content
10.1145/1629435.1629475acmconferencesArticle/Chapter ViewAbstractPublication PagesesweekConference Proceedingsconference-collections
research-article

Cycle count accurate memory modeling in system level design

Published: 11 October 2009 Publication History

Abstract

In this paper, we propose an effective automatic generation approach for a Cycle-Count Accurate Memory Model (CCAMM) from the Clocked Finite State Machine (CFSM) of the Cycle Accurate Memory Model (CAMM). Since memory accesses are gradually dominating system activities, a correct and efficient memory timing model is essential to system-level simulation. In general, a CCAMM provides sufficient timing accuracy with low simulation overhead, and hence is preferred over the Simple Fixed Delay Model (SFDM), which has low accuracy, or the CAMM, which has low performance. Our proposed approach can systematically generate the CCAMM and guarantee correctness. The experimental results show that the generated model is as accurate as the Register Transfer Level (RTL) model while running 100X faster.

References

[1]
S. Pasricha, N. Dutt, and M. Ben-Romdhane, "Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration", in Proceedings of DAC, pp. 113--118, 2004
[2]
Debussy: http://www.springsoft.com.tw/
[3]
SimpleScalar: http://www.simplescalar.com/
[4]
Simple memory simulation: http://www.cse.buffalo.edu/~hzgirgis/memorySimulator/memorySimulator.html
[5]
P. Mishra, P. Grun, N. Dutt and A. Nicolau, "Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language," in Int. Conf. on VLSI Design, pp. 70--75, Jan. 2001.
[6]
L. Benini, Davide Bertozzi, Alessandro Bogliolo, Francesco Menichelli and Mauro Olivieri "MPARM: Exploring the Multi-Processor SoC Design Space with SystemC," Springer J. of VLSI Signal Processing, pp. 196--182, 2005.
[7]
R. Ben Atitallah et al., "An MPSoC performance estimation frame work using transaction level modeling," in IEEE RTCSA, pp. 525--533., Korea, 2007.
[8]
J. Edler and M. D. Hill. Dinero IV Trace-Driven uniprocessor Cache Simulator. http://www.neci.nj.nec.com/homepages/homepages/edler/d4/,1998
[9]
T. Kim and J. Kim. "Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory Access Optimization," IEEE Trans. CAD, vol. 26, no. 1, pp. 142--151, Jan. 2007.
[10]
J. Kim and T. Kim. "Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design," in Proceedings of DAC, pp.105--110, 2005.
[11]
O. Ozturk, M. Kandemir, M. J. Irwin, and S.Tosun. "Multi-level on-chip memory hierarchy design for embedded chip multiprocessors," in Proceedings of the 12th ICPADS, 383--390, 2006. IEEE Computer Society.
[12]
D. Wang, B. Ganesh, N. Tuaycharoen, K. Baynes,A. Jaleel, and B. Jacob. "Dramsim: a memory system simulator," SIGARCH Comput. Archit. News, 33(4):100--107, 2005
[13]
Braun, G., Wieferink, A., Schliebusch, O., Leupers, R. and Meyr, H.: "Processor/memory co-exploration on multiple abstraction levels," in Proceedings of Design Automation&Test in Europe (DATE), pp. 966--971, 2003
[14]
M. Cries "the impact of Recent DRAM Architectures on Embedded Systems Performance", In EUROMICR 26, pp. 282--289, 2000
[15]
C. K. Lo and R. S. Tsay "Automatic Generation of Cycle Accurate and Cycle Count Accurate Transaction Level Bus Models from a Formal Model" in Proceedings of ASPDAC, pp.558--563, 2009

Cited By

View all
  • (2014)DRAM System Simulation Speed-Up by Effective-Cycle SelectionProceedings of the 2014 International Symposium on Computer, Consumer and Control10.1109/IS3C.2014.275(1053-1056)Online publication date: 10-Jun-2014
  • (2013)A basic-block power annotation approach for fast and accurate embedded software power estimation2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2013.6673261(118-123)Online publication date: Oct-2013
  • (2012)A cycle-count-accurate simulation platform with enhanced design exploration capabilityProceedings of the 5th International ICST Conference on Simulation Tools and Techniques10.5555/2263019.2263033(113-118)Online publication date: 19-Mar-2012
  • Show More Cited By

Index Terms

  1. Cycle count accurate memory modeling in system level design

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    CODES+ISSS '09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
    October 2009
    498 pages
    ISBN:9781605586281
    DOI:10.1145/1629435
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 11 October 2009

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. ESL
    2. memory modeling

    Qualifiers

    • Research-article

    Conference

    ESWeek '09
    ESWeek '09: Fifth Embedded Systems Week
    October 11 - 16, 2009
    Grenoble, France

    Acceptance Rates

    Overall Acceptance Rate 280 of 864 submissions, 32%

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)1
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 17 Feb 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2014)DRAM System Simulation Speed-Up by Effective-Cycle SelectionProceedings of the 2014 International Symposium on Computer, Consumer and Control10.1109/IS3C.2014.275(1053-1056)Online publication date: 10-Jun-2014
    • (2013)A basic-block power annotation approach for fast and accurate embedded software power estimation2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2013.6673261(118-123)Online publication date: Oct-2013
    • (2012)A cycle-count-accurate simulation platform with enhanced design exploration capabilityProceedings of the 5th International ICST Conference on Simulation Tools and Techniques10.5555/2263019.2263033(113-118)Online publication date: 19-Mar-2012
    • (2012)A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulationProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228384(127-132)Online publication date: 3-Jun-2012

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media