research-article

Mapping pipelined applications onto heterogeneous embedded systems: a bayesian optimization algorithm based approach

Authors:

Antonino Tumeo,

Lorenzo Camerini,

Christian Pilato,

Pier Luca Lanzi,

Fabrizio Ferrandi,

Donatella SciutoAuthors Info & Claims

CODES+ISSS '09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis

Pages 443 - 452

https://doi.org/10.1145/1629435.1629495

Published: 11 October 2009 Publication History

Abstract

In this paper we propose a flow based on the Bayesian Optimization Algorithm (BOA) for mapping pipelined applications on a heterogeneous multiprocessor platform on Field Programmable Gate Array (FPGA) with customizable processors. BOA is a Probabilistic Model Building Genetic Algorithm (PMBGA) that, substituting the classical mutation and crossover operators with the construction and the sampling of a Bayesian network, is able to identify correlated sub-structures within the problem to be maintained while generating new solutions.

The paper introduces the model adopted for pipelined applications and then shows why BOA fits the problem better than other search algorithms, like Genetic Algorithm (GA), Simulated Annealing (SA) and Tabu Search (TS). We also show that our algorithm is able to cope with data parallel pipelined algorithms. We finally validate our flow on realistic applications like JPEG and ADPCM coding by executing the resulting mapping on our platform.

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Cited By

Tumeo AMinutoli MCastellana VManzano JAmatya VBrooks DWei G(2020)Invited: Software Defined Accelerators From Learning Tools Environment2020 57th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18072.2020.9218489(1-6)Online publication date: Jul-2020
https://doi.org/10.1109/DAC18072.2020.9218489
Mariani GPalermo GZaccaria VSilvano C(2015)DeSpErate++: An Enhanced Design Space Exploration Framework Using Predictive Simulation SchedulingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.237963434:2(293-306)Online publication date: Feb-2015
https://doi.org/10.1109/TCAD.2014.2379634
Javaid HParameswaran SJavaid HParameswaran S(2013)Literature SurveyPipelined Multiprocessor System-on-Chip for Multimedia10.1007/978-3-319-01113-4_2(21-52)Online publication date: 26-Nov-2013
https://doi.org/10.1007/978-3-319-01113-4_2
Show More Cited By

Index Terms

Mapping pipelined applications onto heterogeneous embedded systems: a bayesian optimization algorithm based approach
1. General and reference
  1. Cross-computing tools and techniques
    1. Design

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Published In

cover image ACM Conferences

CODES+ISSS '09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis

October 2009

498 pages

ISBN:9781605586281

DOI:10.1145/1629435

Program Chairs:
Wolfgang Rosenstiel
University of Tübingen, Germany
,
Kazutoshi Wakabayashi
NEC, Japan

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 11 October 2009

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ESWeek '09

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ESWeek '09: Fifth Embedded Systems Week

October 11 - 16, 2009

Grenoble, France

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Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

Tumeo AMinutoli MCastellana VManzano JAmatya VBrooks DWei G(2020)Invited: Software Defined Accelerators From Learning Tools Environment2020 57th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18072.2020.9218489(1-6)Online publication date: Jul-2020
https://doi.org/10.1109/DAC18072.2020.9218489
Mariani GPalermo GZaccaria VSilvano C(2015)DeSpErate++: An Enhanced Design Space Exploration Framework Using Predictive Simulation SchedulingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.237963434:2(293-306)Online publication date: Feb-2015
https://doi.org/10.1109/TCAD.2014.2379634
Javaid HParameswaran SJavaid HParameswaran S(2013)Literature SurveyPipelined Multiprocessor System-on-Chip for Multimedia10.1007/978-3-319-01113-4_2(21-52)Online publication date: 26-Nov-2013
https://doi.org/10.1007/978-3-319-01113-4_2
Chen LBoichat NMitra T(2011)Customized MPSoC synthesis for task sequenceProceedings of the 2011 IEEE 9th Symposium on Application Specific Processors10.1109/SASP.2011.5941072(16-21)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1109/SASP.2011.5941072

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