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Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip

Published: 11 October 2009 Publication History

Abstract

In the near future, generic System-on-Chip (SoC) platforms will be replacing custom designed SoCs. Such generic platforms require a highly flexible interconnect in order to support a wide variety of applications. The ReNoC architecture provides this by allowing power efficient, application specific topologies to be configured on top of a fixed but reconfigurable physical architecture through a mixture of packet switching and physical circuit switching.
The first contribution of this paper is three novel algorithms that, given an abstract description of the application and the physical architecture, 1) synthesize the application specific topologies, 2) map them onto the physical architecture, and 3) create deadlock free, application specific routing algorithms.
The second contribution is a novel physical architecture based on an extended mesh of ReNoC nodes. We apply our algorithms to a mixture of real and synthetic applications and three different physical architectures. Our results show that the different algorithms' performance are highly dependent on the physical architecture. On average, our novel physical architecture reduces power consumption by 58% compared to a conventional Network-on-Chip.

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Cited By

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  • (2023)Adaptive Routing for Hybrid Photonic–Plasmonic (HyPPI) Interconnection Network for Manycore Processors Using DDDAS on the ChipHandbook of Dynamic Data Driven Applications Systems10.1007/978-3-031-27986-7_34(903-925)Online publication date: 6-Sep-2023
  • (2016)Modeling of Gaussian Network-Based Reconfigurable Network-on-Chip DesignsIEEE Transactions on Computers10.1109/TC.2015.247961465:7(2134-2142)Online publication date: 1-Jul-2016
  • (2013)SMARTProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485371(338-343)Online publication date: 18-Mar-2013
  • Show More Cited By

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cover image ACM Conferences
CODES+ISSS '09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
October 2009
498 pages
ISBN:9781605586281
DOI:10.1145/1629435
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 11 October 2009

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Author Tags

  1. configuration
  2. mapping
  3. network-on-chip
  4. routing
  5. synthesis
  6. system-on-chip

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ESWeek '09
ESWeek '09: Fifth Embedded Systems Week
October 11 - 16, 2009
Grenoble, France

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Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

View all
  • (2023)Adaptive Routing for Hybrid Photonic–Plasmonic (HyPPI) Interconnection Network for Manycore Processors Using DDDAS on the ChipHandbook of Dynamic Data Driven Applications Systems10.1007/978-3-031-27986-7_34(903-925)Online publication date: 6-Sep-2023
  • (2016)Modeling of Gaussian Network-Based Reconfigurable Network-on-Chip DesignsIEEE Transactions on Computers10.1109/TC.2015.247961465:7(2134-2142)Online publication date: 1-Jul-2016
  • (2013)SMARTProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485371(338-343)Online publication date: 18-Mar-2013
  • (2012)Reconfigurable Networks-on-ChipIntegrated Optical Interconnect Architectures for Embedded Systems10.1007/978-1-4419-6193-8_7(201-240)Online publication date: 27-Sep-2012
  • (2011)The ReNoC Reconfigurable Network-on-ChipACM Transactions on Embedded Computing Systems10.1145/2043662.204366910:4(1-26)Online publication date: 1-Nov-2011
  • (2011)Analytical derivation of traffic patterns in cache-coherent shared-memory systemsMicroprocessors & Microsystems10.1016/j.micpro.2011.06.00735:7(632-642)Online publication date: 1-Oct-2011
  • (2009)Analytical derivation of traffic patterns in shared memory architectures from Task Graphs2009 NORCHIP10.1109/NORCHP.2009.5397825(1-4)Online publication date: Nov-2009

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