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Addressing design margins through error-tolerant circuits

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Rob AitkenAuthors Info & Claims

DAC '09: Proceedings of the 46th Annual Design Automation Conference

Pages 11 - 12

https://doi.org/10.1145/1629911.1629917

Published: 26 July 2009 Publication History

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Abstract

We review adaptive design techniques with particular emphasis on error-tolerant techniques. We compare and contrast traditional adaptive approaches with error-tolerant techniques and analyze the margins eliminated by each of them. We discuss the applications of the latter to on-chip communication and signal-processing. Finally, we focus on a specific example of an error-tolerant technique for general-purpose computing called Razor.

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Cited By

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Nascimento DGeorgiou KEder KXavier-de-Souza S(2024)Evaluating the Effects of Reducing Voltage Margins for Energy-Efficient Operation of MPSoCsIEEE Embedded Systems Letters10.1109/LES.2023.324062516:1(25-28)Online publication date: Mar-2024
https://doi.org/10.1109/LES.2023.3240625
Wang KZhao HLiu JYin JLi ZQiao S(2023)A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuitsIEICE Electronics Express10.1587/elex.20.2023014520:11(20230145-20230145)Online publication date: 10-Jun-2023
https://doi.org/10.1587/elex.20.20230145
Wang JLiang WNiu YGao LZhang W(2020)Multi-dimensional optimization for approximate near-threshold computingFrontiers of Information Technology & Electronic Engineering10.1631/FITEE.200008921:10(1426-1441)Online publication date: 25-Oct-2020
https://doi.org/10.1631/FITEE.2000089
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Addressing design margins through error-tolerant circuits
1. Hardware

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DAC '09: Proceedings of the 46th Annual Design Automation Conference

July 2009

994 pages

ISBN:9781605584973

DOI:10.1145/1629911

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 26 July 2009

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DAC '09: The 46th Annual Design Automation Conference 2009

July 26 - 31, 2009

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Nascimento DGeorgiou KEder KXavier-de-Souza S(2024)Evaluating the Effects of Reducing Voltage Margins for Energy-Efficient Operation of MPSoCsIEEE Embedded Systems Letters10.1109/LES.2023.324062516:1(25-28)Online publication date: Mar-2024
https://doi.org/10.1109/LES.2023.3240625
Wang KZhao HLiu JYin JLi ZQiao S(2023)A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuitsIEICE Electronics Express10.1587/elex.20.2023014520:11(20230145-20230145)Online publication date: 10-Jun-2023
https://doi.org/10.1587/elex.20.20230145
Wang JLiang WNiu YGao LZhang W(2020)Multi-dimensional optimization for approximate near-threshold computingFrontiers of Information Technology & Electronic Engineering10.1631/FITEE.200008921:10(1426-1441)Online publication date: 25-Oct-2020
https://doi.org/10.1631/FITEE.2000089
Lin YCavallaro J(2018)Energy-efficient Convolutional Neural Networks via Statistical Error Compensated Near Threshold Computing2018 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2018.8351679(1-5)Online publication date: May-2018
https://doi.org/10.1109/ISCAS.2018.8351679
Lin ZChen JChen L(2018)A 65 fps Full-HD Hardware Implementation of HOG, HOF, MBHx, and MBHy for Real-Time Action Recognition2018 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2018.8350912(1-5)Online publication date: 2018
https://doi.org/10.1109/ISCAS.2018.8350912
Lin YZhang SShanbhag N(2018)A Rank Decomposed Statistical Error Compensation Technique for Robust Convolutional Neural Networks in the Near Threshold Voltage RegimeJournal of Signal Processing Systems10.1007/s11265-018-1332-490:10(1439-1451)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1007/s11265-018-1332-4
Lin YZhang SShanbhag N(2016)Variation-Tolerant Architectures for Convolutional Neural Networks in the Near Threshold Voltage Regime2016 IEEE International Workshop on Signal Processing Systems (SiPS)10.1109/SiPS.2016.11(17-22)Online publication date: Oct-2016
https://doi.org/10.1109/SiPS.2016.11
Zhang SShanbhag NMarculescu DLiu F(2015)Reduced Overhead Error Compensation for Energy Efficient Machine Learning KernelsProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840822(15-21)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840822
Zhang SShanbhag N(2015)Reduced overhead error compensation for energy efficient machine learning kernels2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2015.7372544(15-21)Online publication date: Nov-2015
https://doi.org/10.1109/ICCAD.2015.7372544
Zhang XBoussaid FBermak A(2014)32 Bit $\times\,$ 32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands SchedulerIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.225203222:4(759-770)Online publication date: 1-Apr-2014
https://dl.acm.org/doi/10.1109/TVLSI.2013.2252032
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On error correction in macro-based circuits

On error correction in macro-based circuits

Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits

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