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Improving STT MRAM storage density through smaller-than-worst-case transistor sizing

Published: 26 July 2009 Publication History

Abstract

This paper presents a technique to improve the storage density of spin-torque transfer (STT) magnetoresistive random access memory (MRAM) in the presence of significant magnetic tunneling junction (MTJ) write current threshold variability. In conventional design practice, the nMOS transistor within each memory cell is sized to be large enough to carry a current larger than the worst-case MTJ write current threshold, leading to an increasing storage density penalty as the technology scales down. To mitigate such variability-induced storage density penalty, this paper presents a smaller-than-worst-case transistor sizing approach with the underlying theme of jointly considering memory cell transistor sizing and defect tolerance. Its effectiveness is demonstrated using 256Mb STT MRAM design at 45nm node as a test vehicle. Results show that, under a normalized write current threshold deviation of 20%, the overall memory die size can be reduced by more than 20% compared with the conventional worst-case transistor sizing design practice.

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K.-T. Nam et al. Switching properties in spin transper torque MRAM with sub-50nm MTJ size. In Proc. of the 7th Annual Non-Volatile Memory Technology Symposium (NVMTS), pages 49--51, Nov. 2006.
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T. Kawahara et al. 2Mb spin-transfer torque ram (SPRAM) with bit-by-bit bidirectional current write and parallelizing-direction current read. In Proc. of 2007 IEEE International Solid-State Circuits Conference, pages 480--481, Feb. 2007.
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Cited By

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  • (2023)Efficient BCH Code Encoding and Decoding Algorithm With Divisor-Distance-Based Polynomial Division for STT-MRAMIEEE Transactions on Magnetics10.1109/TMAG.2022.314291759:4(1-8)Online publication date: Apr-2023
  • (2023)Sparse Code With Minimum Hamming Distance of Three for Spin-Torque Transfer Magnetic Random Access MemoryIEEE Access10.1109/ACCESS.2023.332425511(114071-114079)Online publication date: 2023
  • (2023)Improving Bit-Error-Rate Performance Using Modulation Coding Techniques for Spin-Torque Transfer Magnetic Random Access MemoryIEEE Access10.1109/ACCESS.2023.326352711(33005-33013)Online publication date: 2023
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      cover image ACM Conferences
      DAC '09: Proceedings of the 46th Annual Design Automation Conference
      July 2009
      994 pages
      ISBN:9781605584973
      DOI:10.1145/1629911
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 26 July 2009

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      Author Tags

      1. STT MRAM
      2. defect tolerance
      3. transistor sizing

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      DAC '09: The 46th Annual Design Automation Conference 2009
      July 26 - 31, 2009
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      Cited By

      View all
      • (2023)Efficient BCH Code Encoding and Decoding Algorithm With Divisor-Distance-Based Polynomial Division for STT-MRAMIEEE Transactions on Magnetics10.1109/TMAG.2022.314291759:4(1-8)Online publication date: Apr-2023
      • (2023)Sparse Code With Minimum Hamming Distance of Three for Spin-Torque Transfer Magnetic Random Access MemoryIEEE Access10.1109/ACCESS.2023.332425511(114071-114079)Online publication date: 2023
      • (2023)Improving Bit-Error-Rate Performance Using Modulation Coding Techniques for Spin-Torque Transfer Magnetic Random Access MemoryIEEE Access10.1109/ACCESS.2023.326352711(33005-33013)Online publication date: 2023
      • (2021)Magnetoresistive Circuits and Systems: Embedded Non-Volatile Memory to Crossbar ArraysIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2021.306968268:6(2281-2294)Online publication date: Jun-2021
      • (2021)Exploring Applications of STT-RAM in GPU ArchitecturesIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2020.303189568:1(238-249)Online publication date: Jan-2021
      • (2019)Design of Rate-Compatible Protograph LDPC Codes for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM)IEEE Access10.1109/ACCESS.2019.29598377(182425-182432)Online publication date: 2019
      • (2018)Modeling of biaxial magnetic tunneling junction for multi-level cell STT-RAM realizationProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201701(375-380)Online publication date: 22-Jan-2018
      • (2018)Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAMACM Journal on Emerging Technologies in Computing Systems10.1145/315483614:1(1-20)Online publication date: 8-Mar-2018
      • (2018)Computing in Memory With Spin-Transfer Torque Magnetic RAMIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.277695426:3(470-483)Online publication date: 1-Mar-2018
      • (2018)Modeling of biaxial magnetic tunneling junction for multi-level cell STT-RAM realization2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2018.8297352(375-380)Online publication date: Jan-2018
      • Show More Cited By

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