skip to main content
10.1145/1629911.1629958acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
research-article

Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications

Published: 26 July 2009 Publication History

Abstract

Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propose a low power design technique of gated bus which can greatly reduce power consumption on state-of-the-art bus architectures. By adding demultiplxers and adopting a novel shortest-path Steiner graph, we achieve a flexible tradeoff between large power reduction versus small wire-length increment. According to our experiments, using the gated bus we can reduce on average 93.2% of wire capacitance per transaction, nearly half of bus dynamic power and on a scale of 5%~10% of total system power.

References

[1]
C. J. Alpertt, A. B. Kahng, C. N. Szet, and Q. Wang. Timing-driven Steiner trees are (practically) free. ACM/IEEE Design Automation Conf., pages 389--392, 2006.
[2]
B. Bollobás, D. Coppersmith, and M. Elkin. Sparse distance preservers and additive spanners. SIAM Journal on Discrete Math., pages 1029--1055, 2005.
[3]
M. Caldari, M. Conti, M. Coppola, P. Crippa, S. Orcioni, L. Pieralisi, and C. Turchetti. System-level power analysis methodology applied to the AMBA AHB bus. Design, Automation and Test in Europe: Designers' Forum, 2:20032, 2003.
[4]
J. Y. Chen, W. B. Jone, J. S. Wang, H. I. Lu, and T. F. Chen. Segmented bus design for low power systems. IEEE Trans. VLSI Systems, 7(1):25--29, 1999.
[5]
J. Cong, A. B. Kahng, and K.-S. Leung. Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. IEEE Trans. Computer-Aided Design, 17(1):24--39, Jan. 1998.
[6]
M. Donno, A. Ivaldi, L. Benini, and E. Macii. Clock-tree power optimization based on RTL clock-gating. ACM/IEEE Design Automation Conf., pages 622--627, 2003.
[7]
M. R. Garey and D. S. Johnson. The rectilinear Steiner tree problem is NP-complete. SIAM Journal on Applied Math., 32:826--834, 1977.
[8]
J. Griffith, G. Robins, J. Salowe, and T. Zhang. Closing the gap: Near-optimal Steiner trees in polynomial time. IEEE Trans. Computer-Aided Design, 13:1351--1365, 1994.
[9]
R. Ho, K. W. Mai, and M. A. Horowitz. The future of wires. Proceedings IEEE, 89:490--504, 2001.
[10]
C.-T. Hsieh and M. Pedram. An edge-based heuristic for Steiner routing. IEEE Trans. Computer-Aided Design, 13(12):1563--1568, Dec. 1994.
[11]
C.-T. Hsieh and M. Pedram. Architectural power optimization by bus splitting. Design, Automation and Test in Europe, pages 612--616, 2000.
[12]
K. Lahiri and A. Raghunathan. Power analysis of system-level on-chip communication architectures. Int'l Conf. Hardware-Software Codesign and System Synthesis, pages 236--241, 2004.
[13]
S. Pasricha, Y.-H. Park, F. J. Kurdahi, and N. Dutt. System-level power-performance trade-offs in bus matrix communication architecture synthesis. Int'l Conf. Hardware-Software Codesign and System Synthesis, pages 300--305, 2006.
[14]
M. Powell, S. H. Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar. Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories. Int'l Symp. Low Power Electronics and Design, pages 90--95, 2000.
[15]
S. K. Rao, P. Sadayappan, F. K. Hwang, and P. W. Shor. The rectilinear Steiner arborescence problem. Algorithmica, 7:277--288, 1992.
[16]
S. Rodriguez and B. Jacob. Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm). Int'l Symp. Low Power Electronics and Design, pages 25--30, 2006.
[17]
M. Zachariasen. A catalog of Hanan grid problems. Networks, 38:200--1, 2000.
[18]
AMBA 2.0 specification. http://www.arm.com/products/solutions/AMBA_Spec.html, 1999.
[19]
Coreconnect bus architecture. IBM White Paper, 1999.
[20]
Avalon interface specifications. http://www.altera.com/literature, 2008.

Cited By

View all
  • (2012)Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graphProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160940(105-112)Online publication date: 25-Mar-2012
  • (2011)Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip CommunicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.209717030:2(167-179)Online publication date: 1-Feb-2011
  • (2010)Physical synthesis of bus matrix for high bandwidth low power on-chip communicationsProceedings of the 19th international symposium on Physical design10.1145/1735023.1735049(91-96)Online publication date: 14-Mar-2010

Index Terms

  1. Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    DAC '09: Proceedings of the 46th Annual Design Automation Conference
    July 2009
    994 pages
    ISBN:9781605584973
    DOI:10.1145/1629911
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 26 July 2009

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. Steiner graph
    2. gated bus
    3. power efficiency

    Qualifiers

    • Research-article

    Funding Sources

    Conference

    DAC '09
    Sponsor:
    DAC '09: The 46th Annual Design Automation Conference 2009
    July 26 - 31, 2009
    California, San Francisco

    Acceptance Rates

    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

    Upcoming Conference

    DAC '25
    62nd ACM/IEEE Design Automation Conference
    June 22 - 26, 2025
    San Francisco , CA , USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)1
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 25 Feb 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2012)Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graphProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160940(105-112)Online publication date: 25-Mar-2012
    • (2011)Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip CommunicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.209717030:2(167-179)Online publication date: 1-Feb-2011
    • (2010)Physical synthesis of bus matrix for high bandwidth low power on-chip communicationsProceedings of the 19th international symposium on Physical design10.1145/1735023.1735049(91-96)Online publication date: 14-Mar-2010

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media