research-article

Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications

Authors:

Chung-Kuan ChengAuthors Info & Claims

DAC '09: Proceedings of the 46th Annual Design Automation Conference

Pages 166 - 171

https://doi.org/10.1145/1629911.1629958

Published: 26 July 2009 Publication History

Abstract

Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propose a low power design technique of gated bus which can greatly reduce power consumption on state-of-the-art bus architectures. By adding demultiplxers and adopting a novel shortest-path Steiner graph, we achieve a flexible tradeoff between large power reduction versus small wire-length increment. According to our experiments, using the gated bus we can reduce on average 93.2% of wire capacitance per transaction, nearly half of bus dynamic power and on a scale of 5%~10% of total system power.

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Cited By

Cheng CDu PKahng AWeng SHu JKoh C(2012)Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graphProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160940(105-112)Online publication date: 25-Mar-2012
https://dl.acm.org/doi/10.1145/2160916.2160940
Wang RZhang YChou NYoung ECheng CGraham R(2011)Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip CommunicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.209717030:2(167-179)Online publication date: 1-Feb-2011
https://dl.acm.org/doi/10.1109/TCAD.2010.2097170
Wang RYoung EGraham RCheng CSaxena PChang Y(2010)Physical synthesis of bus matrix for high bandwidth low power on-chip communicationsProceedings of the 19th international symposium on Physical design10.1145/1735023.1735049(91-96)Online publication date: 14-Mar-2010
https://dl.acm.org/doi/10.1145/1735023.1735049

Index Terms

Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
1. Applied computing
  1. Physical sciences and engineering
    1. Engineering

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cover image ACM Conferences

DAC '09: Proceedings of the 46th Annual Design Automation Conference

July 2009

994 pages

ISBN:9781605584973

DOI:10.1145/1629911

Copyright © 2009 ACM.

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems

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New York, NY, United States

Publication History

Published: 26 July 2009

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DAC '09: The 46th Annual Design Automation Conference 2009

July 26 - 31, 2009

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Cheng CDu PKahng AWeng SHu JKoh C(2012)Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graphProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160940(105-112)Online publication date: 25-Mar-2012
https://dl.acm.org/doi/10.1145/2160916.2160940
Wang RZhang YChou NYoung ECheng CGraham R(2011)Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip CommunicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.209717030:2(167-179)Online publication date: 1-Feb-2011
https://dl.acm.org/doi/10.1109/TCAD.2010.2097170
Wang RYoung EGraham RCheng CSaxena PChang Y(2010)Physical synthesis of bus matrix for high bandwidth low power on-chip communicationsProceedings of the 19th international symposium on Physical design10.1145/1735023.1735049(91-96)Online publication date: 14-Mar-2010
https://dl.acm.org/doi/10.1145/1735023.1735049

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