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Speedpath analysis based on hypothesis pruning and ranking

Published: 26 July 2009 Publication History

Abstract

In optimizing high-performance designs, speed limiting paths (speed-paths) impact the performance and power trade-off. Timing tools attempt to model and capture all such paths on a chip. Due to the high performance nature of these designs, critical paths predicted by the timing tools often do not match the actual speedpaths found on silicon chips. Early silicon data therefore is used to identify the speedpaths, and further performance optimization is carried out by pushing the delays on these paths. In this context, the paper presents a novel data mining approach that analyzes a small number of identified speedpaths against a large number of non-speedpaths. The result of this analysis for each speedpath is a set of hypotheses explaining why the path is special. These hypotheses can be used in guiding the search for the root causes, or in predicting additional paths as potential speedpaths. We demonstrate the feasibility of this approach and summarize our findings based on analysis of silicon speedpaths collected from a 65nm microprocessor.

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Cited By

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  • (2019)Silicon Proven Timing Signoff Methodology using Hazard-Free Robust Path Delay Tests2019 IEEE 37th VLSI Test Symposium (VTS)10.1109/VTS.2019.8758603(1-6)Online publication date: Apr-2019
  • (2012)Speed-path analysis for multi-path failed latches with random variationThirteenth International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2012.6187547(545-552)Online publication date: Mar-2012
  • (2011)Post-silicon failing-test generation through evolutionary computation2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip10.1109/VLSISoC.2011.6081667(164-167)Online publication date: Oct-2011
  • Show More Cited By

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    cover image ACM Conferences
    DAC '09: Proceedings of the 46th Annual Design Automation Conference
    July 2009
    994 pages
    ISBN:9781605584973
    DOI:10.1145/1629911
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 26 July 2009

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    Author Tags

    1. data mining
    2. speedpath
    3. timing analysis

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    • CAMicro/Intel project

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    DAC '09
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    DAC '09: The 46th Annual Design Automation Conference 2009
    July 26 - 31, 2009
    California, San Francisco

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    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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    View all
    • (2019)Silicon Proven Timing Signoff Methodology using Hazard-Free Robust Path Delay Tests2019 IEEE 37th VLSI Test Symposium (VTS)10.1109/VTS.2019.8758603(1-6)Online publication date: Apr-2019
    • (2012)Speed-path analysis for multi-path failed latches with random variationThirteenth International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2012.6187547(545-552)Online publication date: Mar-2012
    • (2011)Post-silicon failing-test generation through evolutionary computation2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip10.1109/VLSISoC.2011.6081667(164-167)Online publication date: Oct-2011
    • (2011)Automatic Generation of Software-based Functional Failing Test for Speed Debug and On-silicon Timing VerificationProceedings of the 2011 12th International Workshop on Microprocessor Test and Verification10.1109/MTV.2011.19(51-55)Online publication date: 5-Dec-2011
    • (2011)Artificial evolution in computer aided design: from the optimization of parameters to the creation of assembly programsComputing10.1007/s00607-011-0157-993:2-4(103-120)Online publication date: 1-Dec-2011
    • (2010)Data learning based diagnosisProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899775(247-254)Online publication date: 18-Jan-2010
    • (2010)Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatchProceedings of the 47th Design Automation Conference10.1145/1837274.1837368(374-379)Online publication date: 13-Jun-2010
    • (2010)Mining AC delay measurements for understanding speed-limiting paths2010 IEEE International Test Conference10.1109/TEST.2010.5699258(1-10)Online publication date: Nov-2010
    • (2010)On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon ValidationProceedings of the 2010 19th IEEE Asian Test Symposium10.1109/ATS.2010.50(243-248)Online publication date: 1-Dec-2010
    • (2010)Data learning based diagnosis2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2010.5419888(247-254)Online publication date: Jan-2010
    • Show More Cited By

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