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A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors

Published: 26 July 2009 Publication History

Abstract

We present a voltage-scalable and process-variation resilient memory architecture, suitable for MPEG-4 video processors such that power dissipation can be traded for graceful degradation in "quality". The key innovation in our proposed work is a hybrid memory array, which is mixture of conventional 6T and 8T SRAM bit-cells. The fundamental premise of our approach lies in the fact that human visual system (HVS) is mostly sensitive to higher order bits of luminance pixels in video data. We implemented a preferential storage policy in which the higher order luma bits are stored in robust 8T bit-cells while the lower order bits are stored in conventional 6T bit-cells. This facilitates aggressive scaling of supply voltage in memory as the important luma bits, stored in 8T bit-cells, remain relatively unaffected by voltage scaling. The not-so-important lower order luma bits, stored in 6T bit-cells, if affected, contribute insignificantly to the overall degradation in output video quality. Simulation results show average power savings of up to 56%, in the hybrid memory array compared to the conventional 6T SRAM array implemented in 65nm CMOS. The area overhead and maximum output quality degradation (PSNR) incurred were 11.5% and 0.56 dB, respectively.

References

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C. Lin et. al. "A 5mW MPEG4 SP Encoder with 2D Bandwidth-Sharing Motion Estimation for Mobile Application", ISSCC Dig. Tech. Papers, Feb., 2006
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G. V. Varatkar, N. Shanbhag. "Variation-Tolerant Motion Estimation Architecture", IWSPS, 2007
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L. Chang et al., "An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches", IEEE Journal of Solid State Circuits, Vol. 44, No. 4, pp. 956--963, 2008
[6]
I. J. Chang et al., "Fast and Accurate Estimation of Nano-Scaled SRAM Read Failure Probability using Critical Point Sampling", Custom Integrated Circuit Conference (CICC), pp 439--442, Sep. 2005
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K. Takeda et al., "Redefinition of write margin for next-generation SRAM and write-margin monitoring circuit", ISSCC Dig. Tech. Papers, pp. 630--631, Feb. 2006
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Y. Lin et al., "A 242mW 10mm2 1080p H.264/AVC High-Profile Encoder Chip", ISSCC Dig. Tech. Papers, Feb. 2008
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T. Liu et al., "A 125 μW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile applications", IEEE Journal of Solid State Circuits, Vol. 42, No. 1, pp. 161--169, 2007
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I. J. Chang et. al, "A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS", ISSCC Dig. Tech. Papers, pp. 388--389, Feb. 2008
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  • (2025)A New Low-Power Circuit Design Optimization for Image ProcessingElectronics10.3390/electronics1402027714:2(277)Online publication date: 11-Jan-2025
  • (2017)Evaluating Data Resilience in CNNs from an Approximate Memory PerspectiveProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060435(89-94)Online publication date: 10-May-2017
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  1. A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors

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    cover image ACM Conferences
    DAC '09: Proceedings of the 46th Annual Design Automation Conference
    July 2009
    994 pages
    ISBN:9781605584973
    DOI:10.1145/1629911
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 26 July 2009

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    Author Tags

    1. graceful degradation
    2. low power SRAM
    3. supply voltage over-scaling

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    • Focused Center Research Program (GSRC)

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    DAC '09: The 46th Annual Design Automation Conference 2009
    July 26 - 31, 2009
    California, San Francisco

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    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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    Cited By

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    • (2025)A New Low-Power Circuit Design Optimization for Image ProcessingElectronics10.3390/electronics1402027714:2(277)Online publication date: 11-Jan-2025
    • (2017)Evaluating Data Resilience in CNNs from an Approximate Memory PerspectiveProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060435(89-94)Online publication date: 10-May-2017
    • (2016)A Multi-accuracy-Level Approximate Memory Architecture Based on Data Significance Analysis2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2016.84(385-390)Online publication date: Jul-2016
    • (2014)VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP ApplicationsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2013.229109161:2(120-124)Online publication date: Feb-2014
    • (2014)Low-cost scratchpad memory organizations using heterogeneous cell sizes for low-voltage operationsMicroprocessors and Microsystems10.1016/j.micpro.2014.06.00238:7(707-716)Online publication date: Oct-2014
    • (2013)Ten Years of Building Broken ChipsACM Transactions on Embedded Computing Systems10.1145/2465787.246578912:2s(1-23)Online publication date: 1-May-2013
    • (2013)Techniques for compensating memory errors in JPEG2000IEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.218040721:1(159-163)Online publication date: 1-Jan-2013
    • (2013)Energy and Quality-Aware Multimedia Signal ProcessingIEEE Transactions on Multimedia10.1109/TMM.2013.226609415:7(1579-1593)Online publication date: 1-Nov-2013
    • (2012)Quality-Aware Techniques for Reducing Power of JPEG CodecsJournal of Signal Processing Systems10.1007/s11265-012-0667-569:3(227-237)Online publication date: 1-Dec-2012
    • (2012)Reducing SRAM Power Using Fine-Grained Wordline Pulse Width ControlNanometer Variation-Tolerant SRAM10.1007/978-1-4614-1749-1_4(97-117)Online publication date: 26-Sep-2012
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