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Optimum LDPC decoder: a memory architecture problem

Authors:

Erick Amador,

Renaud Pacalet,

Vincent RezardAuthors Info & Claims

DAC '09: Proceedings of the 46th Annual Design Automation Conference

Pages 891 - 896

https://doi.org/10.1145/1629911.1630141

Published: 26 July 2009 Publication History

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Abstract

This paper addresses a frequently overlooked problem: designing a memory architecture for an LDPC decoder. We analyze the requirements to support the codes defined in the IEEE 802.11n and 802.16e standards. We show a design methodology for a flexible memory subsystem that reconciles design cost, energy consumption and required latency on a multistandard platform. We show results after exploring the design space on a CMOS technology of 65nm and analyze various use cases from the standardized codes. Comparisons among representative work reveal the benefits of our exploration.

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Nadal JBrown SDupraz ELeduc-Primeau F(2021)Towards an Accurate High-Level Energy Model for LDPC Decoders2021 11th International Symposium on Topics in Coding (ISTC10.1109/ISTC49272.2021.9594187(1-5)Online publication date: 30-Aug-2021
https://doi.org/10.1109/ISTC49272.2021.9594187
Petrovic VMarkovic MEl Mezeni DSaranovac LRadosevic A(2020)Flexible High Throughput QC-LDPC Decoder With Perfect Pipeline Conflicts Resolution and Efficient Hardware UtilizationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2020.3018048(1-14)Online publication date: 2020
https://doi.org/10.1109/TCSI.2020.3018048
Boncalo OAmaricai A(2020)Layered LDPC decoder in-order message access scheduling: a case study2020 IEEE 14th International Symposium on Applied Computational Intelligence and Informatics (SACI)10.1109/SACI49304.2020.9118787(000193-000198)Online publication date: May-2020
https://doi.org/10.1109/SACI49304.2020.9118787
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DAC '09: Proceedings of the 46th Annual Design Automation Conference

July 2009

994 pages

ISBN:9781605584973

DOI:10.1145/1629911

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 26 July 2009

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DAC '09: The 46th Annual Design Automation Conference 2009

July 26 - 31, 2009

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Nadal JBrown SDupraz ELeduc-Primeau F(2021)Towards an Accurate High-Level Energy Model for LDPC Decoders2021 11th International Symposium on Topics in Coding (ISTC10.1109/ISTC49272.2021.9594187(1-5)Online publication date: 30-Aug-2021
https://doi.org/10.1109/ISTC49272.2021.9594187
Petrovic VMarkovic MEl Mezeni DSaranovac LRadosevic A(2020)Flexible High Throughput QC-LDPC Decoder With Perfect Pipeline Conflicts Resolution and Efficient Hardware UtilizationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2020.3018048(1-14)Online publication date: 2020
https://doi.org/10.1109/TCSI.2020.3018048
Boncalo OAmaricai A(2020)Layered LDPC decoder in-order message access scheduling: a case study2020 IEEE 14th International Symposium on Applied Computational Intelligence and Informatics (SACI)10.1109/SACI49304.2020.9118787(000193-000198)Online publication date: May-2020
https://doi.org/10.1109/SACI49304.2020.9118787
Rehman SAwan SMumtaz FRaja M(2019)A novel application of breadth first algorithm for achieving collision free memory mappingPLOS ONE10.1371/journal.pone.021949014:8(e0219490)Online publication date: 15-Aug-2019
https://doi.org/10.1371/journal.pone.0219490
Boncalo OKolumban-Antal GAmaricai ASavin VDeclercq D(2019)Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards MitigationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2018.288425266:4(1643-1656)Online publication date: Apr-2019
https://doi.org/10.1109/TCSI.2018.2884252
Condo CBaghdadi AMasera G(2015)Reducing the Dissipated Energy in Multi-standard Turbo and LDPC DecodersCircuits, Systems, and Signal Processing10.1007/s00034-014-9915-134:5(1571-1593)Online publication date: 1-May-2015
https://dl.acm.org/doi/10.1007/s00034-014-9915-1
Awais MMasera GMartina MMontorsi G(2014)VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief PropagationIEEE Transactions on Signal Processing10.1109/TSP.2014.233080462:15(3965-3975)Online publication date: Aug-2014
https://doi.org/10.1109/TSP.2014.2330804

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