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A randomized interleaved DRAM architecture for the maintenance of exact statistics counters

Published: 16 October 2009 Publication History

Abstract

We extend a previously proposed randomized interleaved DRAM architecture [1] that can maintain wirespeed updates (say 40 Gb/s) to a large array (say millions) of counters. It works by interleaving updates to randomly distributed counters across multiple memory banks. Though unlikely, an adversary can conceivably overload a memory bank by triggering frequent updates to the same counter. In this work, we show this "attack" can be mitigated through caching pending updates, which can catch repeated updates to the same counter within a sliding time window. While this architecture of combining randomization with caching is simple and straightforward, the primary contribution of this work is to rigorously prove that it can handle with overwhelming probability all adversarial update patterns, using a combination of tail bound techniques, convex ordering theory, and queueing analysis.

References

[1]
B. Linand J.Xu, "DRAM is Plenty Fast for Wirespeed Statistics Counting," ACM HotMetrics'08, June 2008.
[2]
A. Muller, D. Stoyan. "Comparison Methods for Stochastic Models and Risks". Wiley, 2002.

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  1. A randomized interleaved DRAM architecture for the maintenance of exact statistics counters

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    Published In

    cover image ACM SIGMETRICS Performance Evaluation Review
    ACM SIGMETRICS Performance Evaluation Review  Volume 37, Issue 2
    September 2009
    89 pages
    ISSN:0163-5999
    DOI:10.1145/1639562
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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 16 October 2009
    Published in SIGMETRICS Volume 37, Issue 2

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    Author Tags

    1. convex ordering
    2. statistics counters
    3. tail bound

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