Kee Beom Kim
ABSTRACT
The communication efficiency plays a crucial role in achieving high system performance in many multimedia SoCs (System-On-Chips). Increased requirements on high bandwidth on-chip communication have led to the emergence of complicated communication architectures and algorithms. However, without thorough analysis of bandwidth requirements of applications, we tend to over-provision resources to avoid potential performance degradation. In this paper, we present a CBR-based traffic modeling technique along with a performance evaluation framework. By using this evaluation technique, we can estimate the sustained performance of on-chip communication infrastructure used in multimedia SoCs. The traffic behaviors of a multimedia application have been captured and analyzed to characterize individual operations which are modeled using traffic generators to replace hardware IPs in evaluation process. The simulation results show that this approach is also effective in discovering the peak performance of on-chip network and bandwidth allocation to IPs.
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Index Terms
- Performance evaluation of on-chip interconnect IP using CBR traffic generator model
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