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CUDA renderer: a programmable graphics pipeline

Published: 16 December 2009 Publication History

Abstract

Modern GPUs provide gradually increasing programmability on vertex shader, geometry shader and fragment shader in the past decade. However, many classical problems such as order-independent transparency (OIT), occlusion culling have not yet been efficiently solved using the traditional graphics pipeline. The main reason is that the behavior of the current stage of the pipeline is hard to be determined due to the unpredictable future data. Since the rasterization and blending stage are still largely fixed functions on chip, previous improvements on these problems always require hardware modifications thus remain on the theoretical level. In this paper we propose CUDA Renderer, a fully programmable graphics pipeline using compute unified device architecture (CUDA) [NVIDIA 2008] which can completely run on current graphics hardware. Our experimental results have demonstrated significant speedup to traditional graphics pipeline especially on OIT. We believe many other problems can also benefit from this flexible architecture.

References

[1]
Hasselgren, J., Munkberg, J., and Akenine-Möller, T. 2009. Automatic pre-tessellation culling. ACM Transactions on Graphics 28, 2.
[2]
Liu, F., Huang, M.-C., Liu, X.-H., and Wu, E.-H. 2009. Single pass depth peeling via cuda rasterizaer. ACM SIGGRAPH 2009 Technical Talk Program.
[3]
NVIDIA. 2008. Nvidia cuda: Compute unified device architecture.

Cited By

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  • (2023)Module-based scientific physics engine architecturePROBLEMS IN PROGRAMMING10.15407/pp2023.03.030(30-39)Online publication date: Sep-2023
  • (2021)A 3D graphics rendering pipeline implementation based on the openCL massively parallel processingThe Journal of Supercomputing10.1007/s11227-020-03581-877:7(7351-7367)Online publication date: 1-Jul-2021
  • (2016)Supporting Static Binding in Stream Rewriting for Heterogeneous Many-Core Architectures2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)10.1109/MCSoC.2016.26(273-280)Online publication date: Sep-2016

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cover image ACM Conferences
SIGGRAPH ASIA '09: ACM SIGGRAPH ASIA 2009 Sketches
December 2009
45 pages
ISBN:9781450379366
DOI:10.1145/1667146
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 16 December 2009

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  • Research-article

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SA09
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SA09: SIGGRAPH ASIA 2009
December 16 - 19, 2009
Yokohama, Japan

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Overall Acceptance Rate 178 of 869 submissions, 20%

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Cited By

View all
  • (2023)Module-based scientific physics engine architecturePROBLEMS IN PROGRAMMING10.15407/pp2023.03.030(30-39)Online publication date: Sep-2023
  • (2021)A 3D graphics rendering pipeline implementation based on the openCL massively parallel processingThe Journal of Supercomputing10.1007/s11227-020-03581-877:7(7351-7367)Online publication date: 1-Jul-2021
  • (2016)Supporting Static Binding in Stream Rewriting for Heterogeneous Many-Core Architectures2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)10.1109/MCSoC.2016.26(273-280)Online publication date: Sep-2016

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