ABSTRACT
Despite flash memory's promise, it suffers from many idiosyncrasies such as limited durability, data integrity problems, and asymmetry in operation granularity. As architects, we aim to find ways to overcome these idiosyncrasies while exploiting flash memory's useful characteristics. To be successful, we must understand the trade-offs between the performance, cost (in both power and dollars), and reliability of flash memory. In addition, we must understand how different usage patterns affect these characteristics. Flash manufacturers provide conservative guidelines about these metrics, and this lack of detail makes it difficult to design systems that fully exploit flash memory's capabilities. We have empirically characterized flash memory technology from five manufacturers by directly measuring the performance, power, and reliability. We demonstrate that performance varies significantly between vendors, devices, and from publicly available datasheets. We also demonstrate and quantify some unexpected device characteristics and show how we can use them to improve responsiveness and energy consumption of solid state disks by 44% and 13%, respectively, as well as increase flash device lifetime by 5.2x.
- Onfi: Open nand flash interface. http://onfi.org/specifications.Google Scholar
- Onfi: Open nand flash interface specification 2.0. http://onfi.org/wp-content/uploads/2009/02/onfi_2_0_gold.pdf.Google Scholar
- Umass trace repository. http://traces.cs.umass.edu/index.php/Storage/Storage.Google Scholar
- International technology roadmap for semiconductors: Emerging research devices, 2007.Google Scholar
- M. Baker, S. Asami, E. Deprit, J. Ouseterhout, and M. Seltzer. Non-volatile memory for fast, reliable file systems. In ASPLOS-V: Proceedings of the fifth international conference on Architectural support for programming languages and operating systems, pages 10--22, New York, NY, USA, 1992. ACM. Google ScholarDigital Library
- A. Birrell, M. Isard, C. Thacker, and T. Wobber. A design for high-performance flash disks. Technical Report MSR-TR-2005-176, Microsoft Research, December 2005.Google Scholar
- e. a. C. Trinh. A 5.6mb/s 64gb 4b/cell nand flash memory in 43nm cmos. In Solid-State Circuits Conference. IEEE, 2009.Google Scholar
- A. M. Caulfield, L. M. Grupp, and S. Swanson. Gordon: using flash memory to build fast, power-efficient clusters for data-intensive applications. SIGPLAN Not., 44(3):217--228, 2009. Google ScholarDigital Library
- L.-P. Chang. On efficient wear leveling for large-scale flash-memory storage systems. In SAC '07: Proceedings of the 2007 ACM symposium on Applied computing, pages 1126--1130, New York, NY, USA, 2007. ACM. Google ScholarDigital Library
- P. Juang, H. Oki, Y. Wang, M. Martonosi, L. S. Peh, and D. Rubenstein. Energy-efficient computing for wildlife tracking: design tradeoffs and early experiences with zebranet. In ASPLOS-X: Proceedings of the 10th international conference on Architectural support for programming languages and operating systems, pages 96--107, New York, NY, USA, 2002. ACM. Google ScholarDigital Library
- D. Jung, Y.-H. Chae, H. Jo, J.-S. Kim, and J. Lee. A group-based wear-leveling algorithm for large-capacity flash memory storage systems. In CASES '07: Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, pages 160--164, New York, NY, USA, 2007. ACM. Google ScholarDigital Library
- T. Kgil, D. Roberts, and T. Mudge. Improving nand flash based disk caches. In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture, pages 327--338, Washington, DC, USA, 2008. IEEE Computer Society. Google ScholarDigital Library
- V. Prabhakaran, T. L. Rodeheffer, and L. Zhou. Transactional flash. USENIX Symposium on Operating Systems Design and Implementation, 2008. Google ScholarDigital Library
- R. Rivest and A. Shamir. How to reuse a write-once memory. Information and control, 55:1--19, December 1982.Google ScholarCross Ref
- e. a. R. W. Zeng. A 172mm2 32gb mlc nand flash memory in 34nm cmos. In Solid-State Circuits Conference. IEEE, 2009.Google Scholar
- e. a. S. Chang. A 48nm 32gb 8-level nand flash memory with 5.5mb/s program throughput. In Solid-State Circuits Conference. IEEE, 2009.Google Scholar
- e. a. T. Futatsuyama. A 113mm2 32gb 3b/cell nand flash memory. In Solid-State Circuits Conference. IEEE, 2009.Google Scholar
- D. Woodhouse. Jffs2: The journalling flash file system, version 2. http://sources.redhat.com/jffs2/.Google Scholar
Recommendations
Next high performance and low power flash memory package structure
In general, NAND flash memory has advantages in low power consumption, storage capacity, and fast erase/write performance in contrast to NOR flash. But, main drawback of the NAND flash memory is the slow access time for random read operations. Therefore,...
NAND flash memory system based on the Harvard buffer architecture for multimedia applications
The main purpose of this research is to design a new memory architecture for NAND flash memory to provide XIP (execute in place) for code execution as well as overcome the biggest bottleneck for data execution. NOR flash for multimedia application is ...
Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices
While NAND flash memory is used in a variety of end-user devices, it has a few disadvantages, such as asymmetric speed of read and write operations, inability to in-place updates, among others. To overcome these problems, various flash-aware strategies ...
Comments