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Reducing peak power with a table-driven adaptive processor core

Published: 12 December 2009 Publication History

Abstract

The increasing power dissipation of current processors and processor cores constrains design options, increases packaging and cooling costs, increases power delivery costs, and decreases reliability. Much research has been focused on decreasing average power dissipation, which most directly addresses cooling costs and reliability. However, much less has been done to decrease peak power, which most directly impacts the processor design, packaging, and power delivery. This research proposes a new architecture which provides a significant decrease in peak power with limited performance loss. It does this through the use of a highly adaptive processor. Many components of the processor can be configured at different levels, but because they are centrally controlled, the architecture can guarantee that they are never all configured maximally at the same time. This paper describes this adaptive processor and explores mechanisms for transitioning between allowed configurations to maximize performance within a peak power constraint. Such an architecture can cut peak power by 25% with less than 5% performance loss; among other advantages, this frees 5.3% of total core area used for decoupling capacitors.

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cover image ACM Conferences
MICRO 42: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
December 2009
601 pages
ISBN:9781605587981
DOI:10.1145/1669112
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 12 December 2009

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Author Tags

  1. adaptive architectures
  2. decoupling capacitance
  3. peak power
  4. resource resizing
  5. voltage variation

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Overall Acceptance Rate 484 of 2,242 submissions, 22%

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  • (2023)Power Management of Multicore SystemsHandbook of Computer Architecture10.1007/978-981-15-6401-7_55-1(1-33)Online publication date: 1-Apr-2023
  • (2021)Bi-Directional Timing-Power Optimisation on Heterogeneous Multi-Core ArchitecturesIEEE Transactions on Sustainable Computing10.1109/TSUSC.2020.30149126:4(572-585)Online publication date: 1-Oct-2021
  • (2019)Supervisory Control Approach and its Symbolic Computation for Power-Aware RT SchedulingIEEE Transactions on Industrial Informatics10.1109/TII.2018.282456415:2(787-799)Online publication date: Feb-2019
  • (2019)Architecting Waferscale Processors - A GPU Case Study2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2019.00042(250-263)Online publication date: Feb-2019
  • (2019)The Impact of Parallel Programming Interfaces on EnergyParallel Computing Hits the Power Wall10.1007/978-3-030-28719-1_3(17-40)Online publication date: 6-Nov-2019
  • (2018)A Case for Packageless Processors2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2018.00047(466-479)Online publication date: Feb-2018
  • (2018)Exploring Power Budget Scheduling Opportunities and Tradeoffs for AMR-Based Applications2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)10.1109/CAHPC.2018.8645941(57-64)Online publication date: Sep-2018
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