skip to main content
10.1145/1687399.1687407acmconferencesArticle/Chapter ViewAbstractPublication PagesiccadConference Proceedingsconference-collections
research-article

How to consider shorts and guarantee yield rate improvement for redundant wire insertion

Published: 02 November 2009 Publication History

Abstract

This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip yield rate improvement for redundant wire insertion. Without considering yield rate degradation caused by shorts, traditional methods may even lead to yield rate loss. However, shorts are more complicated to analyze than opens. Moreover, since any two points of a routed net can be connected by a redundant wire, the number of possible insertion patterns for a chip is un-tractable. To maximize yield rate improvement and to make the problem tractable, we identify a key insight, tolerance-ratio, as an effective guide for choosing insertion patterns and insertion order. Finally, to guarantee yield rate improvement, only positive gain redundant wires are committed. Experimental results show that, compared with unprocessed cases, all yield rate improvements in the proposed algorithm are positive, and the defect rates are reduced by up to 65% and by 24% on average. On the other hand, without considering shorts, the defect rate can increase as much as 7%.

References

[1]
J. W. McPherson, "Reliability Challenges for 45nm and Beyond," Proceedings of the 43rd annual conference on Design automation, 2006, pp. 176--181.
[2]
J. P. de Gyvez, "Yield modeling and BEOL fundamentals," SLIP, 2001, pp. 135--163.
[3]
C-K Hu, "Effects of overlayers on electromigration reliability improvement for Cu/Low-k," IRPS, 2004, pp. 222--228.
[4]
Andrew B. Kahng, Bao Liu, and Ion I. Mandoiu. "Non-tree Routing for Reliability and Yield Improvement," ICCAD, 2002, pp. 260--266.
[5]
P. Panitz, M. Olbrich, E. Barke, and J. Koehl, "Robust Wiring Networks for DfY Considering Timing Constraints," GLSVLSI, 2007, pp. 43--48.
[6]
B. A. McCoy, and G. Robins, "Non-tree routing," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 1995, pp. 790--784.
[7]
Kai-Yuan Chao, Ting-Chi Wang, and Kuang-Yao Lee, "Post-Routing Redundant Via Insertion and Line End," ICCAD, 2006, pp. 633--640.
[8]
Cheok-Kei Lei, Po-Yi Chiang and Yu-Min Lee, "Post-Routing Redundant Via Insertion with Wire Spreading Capability," Proceedings of the 2009 conference on Asia South Pacific design automation, 2009, pp. 468--473.
[9]
J. Bickford, J. Hibbeler, M. Buhler, J. Koehl, D. Muller, S. Peyer and C. Schulte, "Yield Improvement by Local Wiring Redundancy," Proceedings of the 2009 conference on Asia South Pacific design automation., 2009, pp. 468--473.
[10]
Olivier Rizzo, and Hanno Melzner, "Concurrent Wire Spreading, Widening, and Filling," Proceedings of the 44th annual conference on Design automation, 2007, pp. 350--353.
[11]
Minsik Cho, Hua Xiang, Ruchir Puri, and David Z. Pan, "TROY: Track Router with Yield driven Wire Planning," Proceedings of the 44th annual conference on Design automation, 2007, pp. 55--58.
[12]
TSMC Document No. T-N65-CL-DR001.
[13]
TSMC Document No. T-N45-CL-DR001.
[14]
R. Glang, "Defect Size Distribution in VLSI Chips," IEEE Trans. on Semiconductor Manufacturing, 1991, pp 265--269.
[15]
W. Maly, "Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 1985, pp. 166--177.
[16]
D. Frank Hsu, Xiao-Dong Hu, and Guo-Hui Lin, "On Minimum-Weight k-Edge Connected steiner Networks on Metric Spaces," Graphs and Combinatorics, 2000, pp. 275--284.
[17]
Raja Jothi, Balaji Raghavachari, and Subramanian Varadarajan, "A 5/4-approximation algorithm for minimum 2-edge-connectivity," SIGACT, 2003, pp. 725--734.

Cited By

View all
  • (2019)MANAIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.226587832:10(1557-1568)Online publication date: 4-Jan-2019
  • (2018)Testing WiNoC-enabled multicore chips with BIST for wireless interconnectsProceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip10.5555/3306619.3306623(1-8)Online publication date: 4-Oct-2018
  • (2018)Testing WiNoC-Enabled Multicore Chips with BIST for Wireless Interconnects2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS)10.1109/NOCS.2018.8512156(1-8)Online publication date: Oct-2018
  • Show More Cited By

Index Terms

  1. How to consider shorts and guarantee yield rate improvement for redundant wire insertion

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design
    November 2009
    803 pages
    ISBN:9781605588001
    DOI:10.1145/1687399
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 02 November 2009

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. opens
    2. redundant wire insertion
    3. shorts
    4. yield rate

    Qualifiers

    • Research-article

    Funding Sources

    Conference

    ICCAD '09
    Sponsor:

    Acceptance Rates

    Overall Acceptance Rate 457 of 1,762 submissions, 26%

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)1
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 17 Feb 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2019)MANAIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.226587832:10(1557-1568)Online publication date: 4-Jan-2019
    • (2018)Testing WiNoC-enabled multicore chips with BIST for wireless interconnectsProceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip10.5555/3306619.3306623(1-8)Online publication date: 4-Oct-2018
    • (2018)Testing WiNoC-Enabled Multicore Chips with BIST for Wireless Interconnects2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS)10.1109/NOCS.2018.8512156(1-8)Online publication date: Oct-2018
    • (2017)Toward Unidirectional Routing Closure in Advanced Technology NodesIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.10.210(2-12)Online publication date: 2017
    • (2017)Redundant Local-Loop Insertion for Unidirectional RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.265181136:7(1113-1125)Online publication date: Jul-2017
    • (2015)Design Methodology for a Robust and Energy-Efficient Millimeter-Wave Wireless Network-on-ChipIEEE Transactions on Multi-Scale Computing Systems10.1109/TMSCS.2015.24784391:1(33-45)Online publication date: 1-Jan-2015
    • (2013)A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2013.6509592(175-180)Online publication date: Jan-2013

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media