Fong-Yuan Chang
Ren-Song Tsay
ABSTRACT
This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip yield rate improvement for redundant wire insertion. Without considering yield rate degradation caused by shorts, traditional methods may even lead to yield rate loss. However, shorts are more complicated to analyze than opens. Moreover, since any two points of a routed net can be connected by a redundant wire, the number of possible insertion patterns for a chip is un-tractable. To maximize yield rate improvement and to make the problem tractable, we identify a key insight, tolerance-ratio, as an effective guide for choosing insertion patterns and insertion order. Finally, to guarantee yield rate improvement, only positive gain redundant wires are committed. Experimental results show that, compared with unprocessed cases, all yield rate improvements in the proposed algorithm are positive, and the defect rates are reduced by up to 65% and by 24% on average. On the other hand, without considering shorts, the defect rate can increase as much as 7%.
- J. W. McPherson, "Reliability Challenges for 45nm and Beyond," Proceedings of the 43rd annual conference on Design automation, 2006, pp. 176--181. Google Scholar
Digital Library
- J. P. de Gyvez, "Yield modeling and BEOL fundamentals," SLIP, 2001, pp. 135--163. Google ScholarDigital Library
- C-K Hu, "Effects of overlayers on electromigration reliability improvement for Cu/Low-k," IRPS, 2004, pp. 222--228.Google Scholar
- Andrew B. Kahng, Bao Liu, and Ion I. Mandoiu. "Non-tree Routing for Reliability and Yield Improvement," ICCAD, 2002, pp. 260--266. Google ScholarDigital Library
- P. Panitz, M. Olbrich, E. Barke, and J. Koehl, "Robust Wiring Networks for DfY Considering Timing Constraints," GLSVLSI, 2007, pp. 43--48. Google ScholarDigital Library
- B. A. McCoy, and G. Robins, "Non-tree routing," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 1995, pp. 790--784.Google Scholar
- Kai-Yuan Chao, Ting-Chi Wang, and Kuang-Yao Lee, "Post-Routing Redundant Via Insertion and Line End," ICCAD, 2006, pp. 633--640. Google ScholarDigital Library
- Cheok-Kei Lei, Po-Yi Chiang and Yu-Min Lee, "Post-Routing Redundant Via Insertion with Wire Spreading Capability," Proceedings of the 2009 conference on Asia South Pacific design automation, 2009, pp. 468--473. Google ScholarDigital Library
- J. Bickford, J. Hibbeler, M. Buhler, J. Koehl, D. Muller, S. Peyer and C. Schulte, "Yield Improvement by Local Wiring Redundancy," Proceedings of the 2009 conference on Asia South Pacific design automation., 2009, pp. 468--473.Google Scholar
- Olivier Rizzo, and Hanno Melzner, "Concurrent Wire Spreading, Widening, and Filling," Proceedings of the 44th annual conference on Design automation, 2007, pp. 350--353. Google ScholarDigital Library
- Minsik Cho, Hua Xiang, Ruchir Puri, and David Z. Pan, "TROY: Track Router with Yield driven Wire Planning," Proceedings of the 44th annual conference on Design automation, 2007, pp. 55--58. Google ScholarDigital Library
- TSMC Document No. T-N65-CL-DR001.Google Scholar
- TSMC Document No. T-N45-CL-DR001.Google Scholar
- R. Glang, "Defect Size Distribution in VLSI Chips," IEEE Trans. on Semiconductor Manufacturing, 1991, pp 265--269.Google ScholarCross Ref
- W. Maly, "Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 1985, pp. 166--177.Google ScholarDigital Library
- D. Frank Hsu, Xiao-Dong Hu, and Guo-Hui Lin, "On Minimum-Weight k-Edge Connected steiner Networks on Metric Spaces," Graphs and Combinatorics, 2000, pp. 275--284.Google ScholarCross Ref
- Raja Jothi, Balaji Raghavachari, and Subramanian Varadarajan, "A 5/4-approximation algorithm for minimum 2-edge-connectivity," SIGACT, 2003, pp. 725--734.Google Scholar
Index Terms
- How to consider shorts and guarantee yield rate improvement for redundant wire insertion
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