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Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control

Authors:

Vinay Hanumaiah,

Sarma Vrudhula,

Karam S. ChathaAuthors Info & Claims

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

Pages 310 - 313

https://doi.org/10.1145/1687399.1687458

Published: 02 November 2009 Publication History

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Abstract

In this paper a precise formulation of the problem of minimizing the maximum completion time of tasks on a multi-core processor, subject to thermal constraints is presented. The power model used in this work, accounts for the leakage dependence on temperature, while the thermal model is based on the HotSpot model. The general problem is shown to be a non-linear optimization problem that includes cyclic constraints between temperature and power. The derived policy of dynamic frequency and voltage control results in a performance improvement of 19.6% over an optimal policy which performs speed-only control.

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Cited By

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Saha SChakraborty SAgarwal SGangopadhyay RSjalander MMcDonald-Maier K(2023)DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious MulticoreIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2022.322875134:2(718-733)Online publication date: 1-Feb-2023
https://doi.org/10.1109/TPDS.2022.3228751
Yao Y(2023)Game-of-Life Temperature-Aware DVFS Strategy for Tile-Based Chip Many-Core ProcessorsIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2023.324476313:1(58-72)Online publication date: Mar-2023
https://doi.org/10.1109/JETCAS.2023.3244763
Chakraborty SSaha SSjälander MMcdonald-Maier K(2021)Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS MaximizationACM Transactions on Embedded Computing Systems10.1145/347699320:5s(1-25)Online publication date: 17-Sep-2021
https://dl.acm.org/doi/10.1145/3476993
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Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control

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ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

November 2009

803 pages

ISBN:9781605588001

DOI:10.1145/1687399

General Chair:
Jaijeet Roychowdhury
Univ. of California, Berkeley, Berkeley, California

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 02 November 2009

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Division of Computer and Network Systems
Consortium for Embedded Systems

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SIGDA

ICCAD '09: The International Conference on Computer-Aided Design

November 2 - 5, 2009

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Saha SChakraborty SAgarwal SGangopadhyay RSjalander MMcDonald-Maier K(2023)DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious MulticoreIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2022.322875134:2(718-733)Online publication date: 1-Feb-2023
https://doi.org/10.1109/TPDS.2022.3228751
Yao Y(2023)Game-of-Life Temperature-Aware DVFS Strategy for Tile-Based Chip Many-Core ProcessorsIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2023.324476313:1(58-72)Online publication date: Mar-2023
https://doi.org/10.1109/JETCAS.2023.3244763
Chakraborty SSaha SSjälander MMcdonald-Maier K(2021)Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS MaximizationACM Transactions on Embedded Computing Systems10.1145/347699320:5s(1-25)Online publication date: 17-Sep-2021
https://dl.acm.org/doi/10.1145/3476993
Chakraborty SKapoor H(2019)Exploring the Role of Large Centralised Caches in Thermal Efficient Chip DesignACM Transactions on Design Automation of Electronic Systems10.1145/333985024:5(1-28)Online publication date: 28-Jun-2019
https://dl.acm.org/doi/10.1145/3339850
Chakraborty SKapoor H(2018)Analysing the Role of Last Level Caches in Controlling Chip TemperatureIEEE Transactions on Sustainable Computing10.1109/TSUSC.2018.28235423:4(289-305)Online publication date: 1-Oct-2018
https://doi.org/10.1109/TSUSC.2018.2823542
Murray JWettin PPande PShirazi B(2016)Current Research Trends and State-of-the-Art NoC DesignsSustainable Wireless Network-on-Chip Architectures10.1016/B978-0-12-803625-9.00009-1(11-21)Online publication date: 2016
https://doi.org/10.1016/B978-0-12-803625-9.00009-1
Chen HRoy SChakraborty K(2015)DARP-MPACM Transactions on Design Automation of Electronic Systems10.1145/275555821:1(1-21)Online publication date: 2-Dec-2015
https://dl.acm.org/doi/10.1145/2755558
Fan MRong RLiu SQuan G(2015)Energy calculation for periodic multi-core scheduling in system thermal steady state with consideration of leakage and temperature dependencyThe Journal of Supercomputing10.1007/s11227-015-1405-071:7(2565-2584)Online publication date: 1-Jul-2015
https://dl.acm.org/doi/10.1007/s11227-015-1405-0
Huang HChaturvedi VQuan GFan JQiu M(2014)Throughput maximization for periodic real-time systems under the maximal temperature constraintACM Transactions on Embedded Computing Systems10.1145/2544375.254439013:2s(1-22)Online publication date: 27-Jan-2014
https://dl.acm.org/doi/10.1145/2544375.2544390
Marowka A(2014)Energy-Efficient Management of DVFS-Enabled Integrated MicroprocessorsProceedings of the 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing10.1109/PDP.2014.47(236-239)Online publication date: 12-Feb-2014
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Recommendations

Throughput optimal task allocation under thermal constraints for multi-core processors

Latency-Aware Dynamic Voltage and Frequency Scaling on Many-Core Architectures for Data-Intensive Applications

Analysis of dynamic power management on multi-core processors

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