skip to main content
research-article

Hierarchical agent monitoring design approach towards self-aware parallel systems-on-chip

Published:05 March 2010Publication History
Skip Abstract Section

Abstract

Hierarchical agent framework is proposed to construct a monitoring layer towards self-aware parallel systems-on-chip (SoCs). With monitoring services as a new design dimension, systems are capable of observing and reconfiguring themselves dynamically at all levels of granularity, based on application requirements and platform conditions. Agents with hierarchical priorities work adaptively and cooperatively to maintain and improve system performance in the presence of variations and faults. Function partitioning of agents and hierarchical monitoring operations on parallel SoCs are analyzed. Applying the design approach on the Network-on-Chip (NoC) platform demonstrates the design process and benefits using the novel approach.

References

  1. Asanovic, K., Bodik, R., Catanzaro, B. C., Gebis, J. J., Husbands, P., Keutzer, K., Patterson, D. A., Plishker, W. L., Shalf, J., Williams, S. W., and Yelick, K. A. 2006. The landscape of parallel computing research: A view from Berkeley. Tech. rep., University of California, Berkeley.Google ScholarGoogle Scholar
  2. Bell, S., Edwards, B., Amann, J., Conlin, R., Joyce, K., Leung, V., MacKay, J., Reif, M., Bao, L., Brown, J., Mattina, M., Miao, C.-C., Ramey, C., Wentzlaff, D., Anderson, W., Berger, E., Fairbanks, N., Khan, D., Montenegro, F., Stickney, J., and Zook, J. 2008. Tile64 - processor: A 64-core soc with mesh interconnect. In Digest of Technical Papers of the IEEE International Solid-State Circuits Conference (ISSCC'08). IEEE, 88--598.Google ScholarGoogle Scholar
  3. Bernstein, K., Frank, D. J., Gattiker, A. E., Haensch, W., Ji, B. L., Nassif, S. R., Nowak, E. J., Pearson, D. J., and Rohrer, N. J. 2006. High-performance cmos variability in the 65-nm regime and beyond. IBM J. Resear. Devel. 50, 4/5, 433--449. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Dickinson, D., Mosovsky, J., and Houthuysen, S. 2003. Assessing integrated circuit manufacturing for environmental performance and sustainability: a full scale ic business application. In Proceedings of the IEEE International Symposium on Electronics and the Environment. IEEE Computer Society, Los Alamitos, CA, 214--219. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Guang, L. and Jantsch, A. 2006. Adaptive power management for the on-chip communication network. In Proceedings of the 9th EUROMICRO DSD Conference. IEEE Computer Society, Los Alamitos, CA, 649--656. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Guang, L., Nigussie, E., Koskinen, L., and Tenhunen, H. 2009. Autonomous dvfs on supply islands for energy-constrained noc communication. In Proceedings of the 22nd International Conference on Architecture of Computing Systems (ARCS'09). Springer-Verlag, 183--194. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Guang, L., Rantala, P., Nigussie, E., Isoaho, J., and Tenhunen, H. 2008. Low-latency and energy-efficient monitoring interconnect for hierarchical-agent-monitored nocs. In Proceedings of the NORCHIP. 227--232.Google ScholarGoogle Scholar
  8. Gunter, D., Tierney, B., Jackson, K., Lee, J., and Stoufer, M. 2002. Dynamic monitoring of high-performance distributed applications. In Proceedings of the 11th IEEE International Symposium on High Performance Distributed Computing HPDC-11. IEEE Computer Society, Los Alamitos, CA, 163--170. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Haensch, W., Nowak, E. J., Dennard, R. H., Solomon, P. M., Bryant, A., Dokumaci, O. H., Kumar, A., Wang, X., Johnson, J. B., and Fischetti, M. V. 2006. Silicon cmos devices beyond scaling. IBM J. Resear. Devel. 50, 4/5, 339--361. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Hazucha, P., Schrom, G., Hahn, J., Bloechel, B., Hack, P., Dermer, G., Narendra, S., Gardner, D., Karnik, T., De, V., and Borkar, S. 2005. A 233-mhz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package. IEEE J. Solid-State Circ. 40, 4, 838--845.Google ScholarGoogle ScholarCross RefCross Ref
  11. He, S. and Torkelson, M. 1996. A new approach to pipeline fft processor. In Proceedings of the 10th International Parallel Processing Symposium (IPPS'96). IEEE Computer Society, Los Alamitos, CA, 766--770. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Hu, J. and Marculescu, R. 2005. Energy and performance-aware mapping for regular noc architectures. IEEE Trans. CAD 24, 4, 551--562. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. ITRS Technology Working Group. 2007. International technology roadmap for semiconductors—design, 2007 Ed. ITRS Technology Working Group.Google ScholarGoogle Scholar
  14. Jantsch, A. 2003. Modeling Embedded Systems and SoC's: Concurrency and Time in Models of Computation. Morgan Kaufmann Publishers Inc., San Francisco, CA. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. Jesshope, C., Miller, P., and Yantchev, J. 1989. High performance communications in processor networks. In Proceedings of the 16th Annual International Symposium on Computer Architecture. ACM, New York, NY, 150--157. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Keutzer, K., Newton, A., Rabaey, J., and Sangiovanni-Vincentelli, A. 2000. System-level design: orthogonalization of concerns and platform-based design. IEEE Trans. CAD 19, 12, 1523--1543. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Kim, W., Gupta, M., Wei, G.-Y., and Brooks, D. 2008. System level analysis of fast, per-core DVFS using on-chip switching regulators. In Proceedingss of the IEEE 14th International Symposium on High Performance Computer Architecture (HPCA'08). 123--134.Google ScholarGoogle Scholar
  18. Kissler, D., Strawetz, A., Hannig, F., and Teich, J. 2009. Power-efficient reconfiguration control in coarse-grained dynamically reconfigurable architectures. In Revised Selected Papers from PATMOS 2008. Springer-Verlag, 307--317.Google ScholarGoogle Scholar
  19. Kumar, S., Jantsch, A., Soininen, J., Forsell, M., Millberg, M., Berg, J., Tiensyrj, K., and Hemani, A. 2002. A network on chip architecture and design methodology. In Proceedingss of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'02). IEEE Computer Society, Los Alamitos, CA, 117. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Lackey, D., Zuchowski, P., Bednar, T., Stout, D., Gould, S., and Cohn, J. 2002. Managing power and performance for system-on-chip designs using voltage islands. In Proceedingss of the IEEE/ACM International Conference on Computer Aided Design (ICCAD'02). ACM, New York, NY, 195--202. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Lehtonen, T., Liljeberg, P., and Plosila, J. 2007. Online reconfigurable self-timed links for fault tolerant noc. VLSI Des. 13.Google ScholarGoogle Scholar
  22. Lin, H.-L., Lin, H., Chen, Y.-C., and Chang, R. 2004. A novel pipelined fast fourier transform architecture for double rate ofdm systems. In Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS'04). IEEE, 7--11.Google ScholarGoogle Scholar
  23. Marculescu, R. 2004. Energy, fault-tolerance, and scalability issues in designing network-on-chip. Tutorial at ASP-DAC.Google ScholarGoogle Scholar
  24. Ogras, U., Marculescu, R., Choudhary, P., and Marculescu, D. 2007. Voltage-frequency island partitioning for gals-based networks-on-chip. In Proceedings of the 44th ACM/IEEE Design Automation Conference (DAC'07). ACM, New York, NY, 110--115. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. Rabaey, J. M. 2007. Scaling the power wall: Revisiting the low-power design rules. In Proceedings of the International Symposium on System-on-chip (SoC'07).Google ScholarGoogle Scholar
  26. Rantala, P., Isoaho, J., and Tenhunen, H. 2007. Agent-based reconfigurability for fault-tolerance in network-on-chip. In Proceedings of the Engineering of Reconfigurable Systems and Algorithms Conference (ERSA). CSREA Press, 207--210.Google ScholarGoogle Scholar
  27. Rota, S. R. and Almeida Jr., J. R. D. 2004. Run-time monitoring for dependable systems: An approach and a case study. In Proceedings of the 23rd IEEE International Symposium on Reliable Distributed Systems (SRDS'04). IEEE Computer Society, Los Alamitos, CA, 41--49. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. Sangiovanni-Vincentelli, A. 2002. Defining platform-based design. EEDesign of EETimes.Google ScholarGoogle Scholar
  29. Sangiovanni-Vincentelli, A. and Martin, G. 2001. Platform-based design and software design methodology for embedded systems. IEEE Des. Test of Comput. 18, 6, 23--33. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. Schattkowsky, T. and Muller, W. 2004. Model-based design of embedded systems. In Proceedings of the 7th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing. IEEE, 113--128.Google ScholarGoogle Scholar
  31. Shamshiri, S., Lisherness, P., Pan, S.-J., and Cheng, K.-T. 2008. A cost analysis framework for multi-core systems with spares. In Proceedings of the IEEE International Test Conference (ITC'08). 1--8.Google ScholarGoogle Scholar
  32. Shang, L., Peh, L.-S., and Jha, N. 2003. Dynamic voltage scaling with links for power optimization of interconnection networks. In Proceedings of the International Symposium of High Performance Computer Architecture (HPCA'03). IEEE Computer Society, Los Alamitos, CA, 91--102. Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. Soteriou, V. and Peh, L.-S. 2007. Exploring the design space of self-regulating power-aware on/off interconnection networks. IEEE Trans. Parall. Distrib. Syst. 18, 3, 393--408. Google ScholarGoogle ScholarDigital LibraryDigital Library
  34. Stratakos, A. J. 1998. High-efficiency low-voltage DC-DC conversion for portable applications. Ph.D. thesis, University of California, Berkeley.Google ScholarGoogle Scholar
  35. Sylvester, D., Blaauw, D., and Karl, E. 2006. Elastic: An adaptive self-healing architecture for unpredictable silicon. IEEE Des. Test Comput. 23, 6, 484--490. Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. Taylor, M., Kim, J., Miller, J., Wentzlaff, D., Ghodrat, F., Greenwald, B., Hoffman, H., Johnson, P., Lee, J.-W., Lee, W., Ma, A., Saraf, A., Seneski, M., Shnidman, N., Strumpen, V., Frank, M., Amarasinghe, S., and Agarwal, A. 2002. The raw microprocessor: a computational fabric for software circuits and general-purpose programs. IEEE Micro 22, 2, 25--35. Google ScholarGoogle ScholarDigital LibraryDigital Library
  37. Tierno, J., Rylyakov, A., and Friedman, D. 2008. A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 NM SOI. IEEE J. Solid-State Circ. 43, 1, 42--51.Google ScholarGoogle ScholarCross RefCross Ref
  38. Truong, D., Cheng, W., Mohsenin, T., Yu, Z., Jacobson, A., Landge, G., Meeuwsen, M., Watnik, C., Tran, A., Xiao, Z., Work, E., Webb, J., Mejia, P., and Baas, B. 2009. A 167-processor computational platform in 65 nm CMOS. IEEE J. Solid-State Circ. 44, 4, 1130--1144.Google ScholarGoogle ScholarCross RefCross Ref
  39. Vangal, S., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Iyer, P., Singh, A., Jacob, T., Jain, S., Venkataraman, S., Hoskote, Y., and Borkar, N. 2007. An 80-tile 1.28tflops network-on-chip in 65nm CMOS. In Digest of Technical Papers. IEEE International Solid-State Circuits Conference (ISSCC'07). IEEE, International, 98--589.Google ScholarGoogle Scholar
  40. Vangal, S., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Singh, A., Jacob, T., Jain, S., Erraguntla, V., Roberts, C., Hoskote, Y., Borkar, N., and Borkar, S. 2008. An 80-tile sub-100-w teraflops processor in 65-nm CMOS. IEEE J. Solid-State-Circ. 43, 1, 29--41.Google ScholarGoogle ScholarCross RefCross Ref
  41. Wang, H.-S., Zhu, X., Peh, L.-S., and Malik, S. 2002a. Orion: a power-performance simulator for interconnection networks. In Proceedings of the 35th Annual IEEE/ACM International Symposium on Microarchitecture. IEEE Computer Society Press, Los Alamitos, CA, 294--305. Google ScholarGoogle ScholarDigital LibraryDigital Library
  42. Wang, M., Madhyastha, T., Chan, N. H., Papadimitriou, S., and Faloutsos, C. 2002b. Data mining meets performance evaluation: fast algorithms for modeling bursty traffic. In Proceedings of the 18th International Conference on Data Engineering. IEEE Computer Society, Los Alamitos, CA, 507--516. Google ScholarGoogle ScholarDigital LibraryDigital Library
  43. Whisnant, K., Kalbarczyk, Z. T., and Iyer, R. K. 2003. A system model for dynamically reconfigurable software. IBM Syst. J. 42, 1, 45--59. Google ScholarGoogle ScholarDigital LibraryDigital Library
  44. Wibben, J. and Harjani, R. 2007. A high efficiency dc-dc converter using 2nh on-chip inductors. In Proceedings of the IEEE Symposium on VLSI Circuits. 22--23.Google ScholarGoogle Scholar
  45. Zergainoh, N.-E., Baghdadi, A., and Jerraya, A. A. 2005. Hardware/software codesign of on-chip communication architecture for application-specific multiprocessor system-on-chip. J. Embedd. Syst. 1, 1/2, 112--124.Google ScholarGoogle Scholar
  46. Zipf, P. 2008. Applying dynamic reconfiguration for fault tolerance in fine-grained logic arrays. IEEE Trans. VLSI Syst. 16, 2, 134--143. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Hierarchical agent monitoring design approach towards self-aware parallel systems-on-chip

        Recommendations

        Comments

        Login options

        Check if you have access through your login credentials or your institution to get full access on this article.

        Sign in

        Full Access

        • Published in

          cover image ACM Transactions on Embedded Computing Systems
          ACM Transactions on Embedded Computing Systems  Volume 9, Issue 3
          February 2010
          442 pages
          ISSN:1539-9087
          EISSN:1558-3465
          DOI:10.1145/1698772
          Issue’s Table of Contents

          Copyright © 2010 ACM

          Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

          Publisher

          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 5 March 2010
          • Accepted: 1 October 2009
          • Revised: 1 December 2008
          • Received: 1 June 2008
          Published in tecs Volume 9, Issue 3

          Permissions

          Request permissions about this article.

          Request Permissions

          Check for updates

          Qualifiers

          • research-article
          • Research
          • Refereed

        PDF Format

        View or Download as a PDF file.

        PDF

        eReader

        View online with eReader.

        eReader