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High throughput and large capacity pipelined dynamic search tree on FPGA

Published: 21 February 2010 Publication History

Abstract

We propose a pipelined Dynamic Search Tree (pDST) on FPGA which offers high throughput for lookup, insert and delete operations as well as the capability to perform in-place incremental updates. Based on the pipelined 2-3 tree data structure, our pDST supports one lookup per clock cycle and maintains tree balance under continual insert and delete operations. A novel buffered update scheme together with a bi-directional linear pipeline allows the pDST to perform one insert or delete operation per O(log N) cycles (N being the tree capacity) without stalling the lookup operations. Nodes at each pipeline stage are allocated and freed by a free-node chaining mechanism which greatly simplifies the memory management circuit. Our prototype implementation of a 15-level, 32-bit key dual-port pDST requires 192 blocks of 36 Kb BRAMs (64%) and 12.8k LUTs (6.3%) on a Virtex 5 LX330 FPGA. The circuit has a maximum capacity of 96k 32-bit keys and clock rate of 135 MHz, supporting 242 million lookups and concurrently 3.97 million inserts or deletes per second.

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  • (2024)Generalizing Ray Tracing Accelerators for Tree Traversals on GPUs2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00080(1041-1057)Online publication date: 2-Nov-2024
  • (2019)A Novel FPGA-Based High Throughput Accelerator For Binary Search Trees2019 International Conference on High Performance Computing & Simulation (HPCS)10.1109/HPCS48598.2019.9188158(612-619)Online publication date: Jul-2019
  • (2019)Irregular-Program-Based Hash Algorithms2019 IEEE International Conference on Decentralized Applications and Infrastructures (DAPPCON)10.1109/DAPPCON.2019.00024(125-128)Online publication date: Apr-2019
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cover image ACM Conferences
FPGA '10: Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
February 2010
308 pages
ISBN:9781605589114
DOI:10.1145/1723112
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 21 February 2010

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Author Tags

  1. 2-3 tree
  2. b-tree
  3. dynamic update
  4. in-place update
  5. incremental update
  6. ip forwarding
  7. openflow
  8. pipelined tree

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Cited By

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  • (2024)Generalizing Ray Tracing Accelerators for Tree Traversals on GPUs2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00080(1041-1057)Online publication date: 2-Nov-2024
  • (2019)A Novel FPGA-Based High Throughput Accelerator For Binary Search Trees2019 International Conference on High Performance Computing & Simulation (HPCS)10.1109/HPCS48598.2019.9188158(612-619)Online publication date: Jul-2019
  • (2019)Irregular-Program-Based Hash Algorithms2019 IEEE International Conference on Decentralized Applications and Infrastructures (DAPPCON)10.1109/DAPPCON.2019.00024(125-128)Online publication date: Apr-2019
  • (2018)ARMOR: A Recompilation and Instrumentation-Free Monitoring Architecture for Detecting Memory ExploitsIEEE Transactions on Computers10.1109/TC.2018.280781867:8(1092-1104)Online publication date: 1-Aug-2018
  • (2016)High-Performance and Dynamically Updatable Packet Classification Engine on FPGAIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2015.238923927:1(197-209)Online publication date: 1-Jan-2016
  • (2016)A Hybrid CPU+GPU Working-Set Dictionary2016 15th International Symposium on Parallel and Distributed Computing (ISPDC)10.1109/ISPDC.2016.16(56-63)Online publication date: 2016
  • (2016)Parallelizing Latent Semantic Indexing using an FPGA-based architecture2016 IEEE 34th International Conference on Computer Design (ICCD)10.1109/ICCD.2016.7753321(432-435)Online publication date: Oct-2016
  • (2014)LayeredTreesIEEE Transactions on Computers10.1109/TC.2013.10963:12(3039-3052)Online publication date: 1-Dec-2014
  • (2014)Scalable and dynamically updatable lookup engine for decision-trees on FPGA2014 IEEE High Performance Extreme Computing Conference (HPEC)10.1109/HPEC.2014.7040952(1-6)Online publication date: Sep-2014
  • (2013)High-performance architecture for dynamically updatable packet classification on FPGAProceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems10.5555/2537857.2537882(125-136)Online publication date: 21-Oct-2013
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