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Efficient FPGAs using nanoelectromechanical relays

Published: 21 February 2010 Publication History

Abstract

Nanoelectromechanical (NEM) relays are promising candidates for programmable routing in Field-Programmable-Gate Arrays (FPGAs). This is due to their zero leakage and potentially low on-resistance. Moreover, NEM relays can be fabricated using a low-temperature process and, hence, may be monolithically integrated on top of CMOS circuits. Hysteresis characteristics of NEM relays can be utilized for designing programmable routing switches in FPGAs without requiring corresponding routing SRAM cells. Our simulation results demonstrate that the use of NEM relays for programmable routing in FPGAs can simultaneously provide 43.6% footprint area reduction, 37% leakage power reduction, and up to 28% critical path delay reduction compared to traditional SRAM-based CMOS FPGAs at the 22nm technology node.

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  • (2023)Non-Volatile Nano-Electro-Mechanical Switches and Hybrid Circuits in a 16 nm CMOS Back-End-of-Line ProcessIEEE Electron Device Letters10.1109/LED.2022.322170144:1(136-139)Online publication date: Jan-2023
  • (2022)Multi-Layer Nanoelectromechanical (NEM) Memory Switches for Multi-Path RoutingIEEE Electron Device Letters10.1109/LED.2021.313057943:1(162-165)Online publication date: Jan-2022
  • (2022)Electro-Thermally Actuated Non-Volatile Mechanical Memory With CMOS-Level Operation Voltage and Low Contact ResistanceJournal of Microelectromechanical Systems10.1109/JMEMS.2021.312010931:1(87-96)Online publication date: Feb-2022
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    cover image ACM Conferences
    FPGA '10: Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
    February 2010
    308 pages
    ISBN:9781605589114
    DOI:10.1145/1723112
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 21 February 2010

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    Author Tags

    1. CMOS-NEM FPGA
    2. nanoelectromechanical relay

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    • (2023)Non-Volatile Nano-Electro-Mechanical Switches and Hybrid Circuits in a 16 nm CMOS Back-End-of-Line ProcessIEEE Electron Device Letters10.1109/LED.2022.322170144:1(136-139)Online publication date: Jan-2023
    • (2022)Multi-Layer Nanoelectromechanical (NEM) Memory Switches for Multi-Path RoutingIEEE Electron Device Letters10.1109/LED.2021.313057943:1(162-165)Online publication date: Jan-2022
    • (2022)Electro-Thermally Actuated Non-Volatile Mechanical Memory With CMOS-Level Operation Voltage and Low Contact ResistanceJournal of Microelectromechanical Systems10.1109/JMEMS.2021.312010931:1(87-96)Online publication date: Feb-2022
    • (2022)AutoTEAIntegration, the VLSI Journal10.1016/j.vlsi.2022.06.01087:C(231-240)Online publication date: 1-Nov-2022
    • (2022)Single‐Contact, Four‐Terminal Microelectromechanical Relay for Efficient Digital LogicAdvanced Electronic Materials10.1002/aelm.2022005849:1(2200584)Online publication date: 6-Sep-2022
    • (2021)Dynamic Ternary Content-Addressable Memory Is Indeed Promising: Design and Benchmarking Using Nanoelectromechanical Relays2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE51398.2021.9474177(1100-1103)Online publication date: 1-Feb-2021
    • (2021)DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical RelaysIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.311562229:11(1981-1993)Online publication date: Nov-2021
    • (2021)Toward Monolithically Integrated Hybrid CMOS-NEM CircuitsIEEE Transactions on Electron Devices10.1109/TED.2021.312240468:12(6430-6436)Online publication date: Dec-2021
    • (2021)Design Technology Co-Optimization for Back-End-of-Line Nonvolatile NEM Switch ArraysIEEE Transactions on Electron Devices10.1109/TED.2021.306225168:4(1471-1477)Online publication date: Apr-2021
    • (2021)3D Integrated CMOS-NEM Systems: Enabling Next-Generation Computing Technology2021 IEEE International Meeting for Future Electron Devices, Kansai (IMFEDK)10.1109/IMFEDK53601.2021.9637634(1-4)Online publication date: 17-Nov-2021
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