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Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only)

Published: 21 February 2010 Publication History

Abstract

Many compute-bound software applications have seen order-of-magnitude speedups using application-specific accelerators built on specialized architectures such as field-programmable gate arrays. These architectures are particularly good at implementing systems of recurrence equations realized as systolic arrays. We pursue high-level synthesis tools for recurrence equations that can search the space of possible parallel array designs to optimize various design criteria. Most existing approaches produce an array that is latency-space optimal. We target applications that operate on a large collection of small inputs, e.g. a database of biological sequences. For these applications, overall throughput, rather than latency per input, is the most important measure of performance.
In this work we introduce a new design space exploration procedure to optimize throughput of a systolic array subject to area and bandwidth constraints of an FPGA device. We show that the throughput of an array is dependent on the maximum number of lattice points executed by any processor in the array, which is determined solely by the array's projection vector. We describe a bounded search process to find throughput-optimized projection vectors, discovering a range of array designs that are optimal for inputs of various sizes.
We have written a tool in C++ that accepts recurrence descriptions and produces throughput-optimized array mappings. We have applied our technique to the banded Smith-Waterman and Nussinov RNA folding algorithms, and present novel arrays that are 4-33x and 2-14x faster, respectively, than the currently-used latency-optimized array.

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cover image ACM Conferences
FPGA '10: Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
February 2010
308 pages
ISBN:9781605589114
DOI:10.1145/1723112

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 February 2010

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Author Tags

  1. dynamic programming
  2. fpga
  3. recurrences
  4. systolic array
  5. throughput optimization

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Overall Acceptance Rate 125 of 627 submissions, 20%

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