Hua Xiang
ABSTRACT
A symmetric-function fan-in tree (SFFT) is a fanout-free cone of logic that computes a symmetric function, so that all of the leaf nets in its support set are commutative. Such trees are frequently found in designs, especially when the design originated as two-level logic.
These trees are usually created during logic synthesis, when there is no knowledge of the locations of the tree root or of the source gates of the leaf nets. Because of this, large SFFTs present a challenge to placement algorithms. The result is that the tree placements are generally far from optimal, leading to wiring congestion, excess buffering, and timing problems. Restructuring such trees can produce a more placeable and wire-efficient design.
In this paper, we propose algorithms to identify and to restructure SFFTs during physical design. The key feature of an SFFT is that it can be implemented with various structures of a uniform set of gates with commutative inputs, i.e. AND, OR, or XOR. Drawing on the flexibility of SFFT logic structures, the proposed tree restructuring algorithm uses existing placement information to rebuild the SFFTs with reduced tree wire lengths. The experimental results demonstrate the efficiency and effectiveness of the algorithms.
- C. J. Alpert, C. Chu, and P. G. Villarrubia, The Comming of Age of Physical Synthesis, In Proc. ICCAD, pp. 246--249, Nov. 2007. Google Scholar
Digital Library
- C. J. Alpert, S. Karandikar, Z. Li, G. J. Nam, S. Quay, H. Ren, C. Sze, P. Villarrubia, and M. Yildiz, The Nuts and Bolts of Physical Synthesis, In Proc. International Workshop on System Level Interconnect Prediction, pp. 89--94, 2007. Google ScholarDigital Library
- C. W. Chang, M. F. Hsiao, B. Hu, K. Wang, M. Marek-Sadowska, C. H. Cheng, and S. J. Chen, Fast Postplacement Optimization Using Functional Symmetries, IEEE Trans. on CAD, pp. 102--118, Jan. 2004. Google ScholarDigital Library
- C. W. Chang and M. Marek-Sadowska, Single-Pass Redundancy Addition and Removal, ICCAD, pp. 606--609, Nov. 2001. Google ScholarDigital Library
- K.-H. Chang, I. L. Markov, V. Bertacco, Post-placement rewiring and rebuffering by exhaustive search for functional symmetries., ICCAD, pp 56--63, 2005. Google ScholarDigital Library
- S. C. Chang, L. P. P. P. van Ginneken, M. Marek-Sadowska, Circuit optimization by rewiring, IEEE Transaction on Computers, pp. 962--969, Sep. 1999. Google ScholarDigital Library
- J. Cong and W. Long, Theory and Algorithm for SPFD-Based Global Rewiring, IWLS, pp.150--155, June 2001.Google Scholar
- P. T. Darga, M. H. Liffiton, K. A. Sakallah, and I. L. Markov, Exploiting Structure in Symmetry Detection for CNF, pp. 530--534, DAC, 2004. Google ScholarDigital Library
- K. Keutzer, A. R. Newton, and N. Shenoy, The future of logic synthesis and physical design in deep-submicron process geometries, Proc. International Symposium on Physical Design, pp 218--224, 1997. Google ScholarDigital Library
- T. Kutzschebauch, and L. Stok, Congestion Aware Layout Driven Logic Synthesis, In Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, Nov. 2001. Google ScholarDigital Library
- J. Lipman, Current chip design flow is flawed, http://www.edadesignline.com/showArticle.jthml?articleID=192200410.Google Scholar
- A. Mishchenko, Fast Computation of Symmetries in Boolean Functions, IEEE Trans. on CAD, pp. 1588--1593, Nov. 2003. Google ScholarDigital Library
- D. Pandini, L. T. Pileggi, and A. J. Strojwas, Congestion-Aware Logic Synthesis, In Proc. DATE, Mar. 2002. Google ScholarDigital Library
- M. Pedram, and N. Bhat, Layout Driven Logic Restructuring Decomposition. In Proc. ICCAD, pages 134--137, Nov. 1991.Google ScholarCross Ref
- R. Shelar, S. Sapatnekar, P. Saxena, and X. Wang, An Efficient Technology Mapping Algorithm Targeting Routing Congestion under Delay Constraints. In Proc. ISPD, pages 210--217, April 2005. Google ScholarDigital Library
- L. Trevillyan, D. Kung, R. Puri, L. N. Reddy, M. A. Kazda, An Integrated Environment for Technology Closure of Deep--Submicron IC Designs, IEEE Design and Test of Computers, Vol.21, pp. 14--22, 2004. Google ScholarDigital Library
Index Terms
- Logical and physical restructuring of fan-in trees
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