Watermarking for JPEG2000 compression standard on FPGA

With the result of advancement in today's technology, digital content can be easily copied, modified, or distributed. Digital watermarking provides the solution to this problem. Most of the digital watermarking methods are divided into two categories: Robust watermarking and fragile watermarking. As a special subset of fragile watermarking, reversible watermarking (lossless or invertible watermarking) enables us to recover the image which is same as the original image pixel by pixel after the content is authenticated. This type of lossless recovery is compulsory in sensitive imagery applications like medical and military purposes.

An efficient watermarking algorithm has been implemented using Matlab which uses the concept of difference expansion of high pass transform coefficients with watermark bits. This work was to find a reversible watermarking algorithm for JPEG2000 standard for medical applications, a (5, 3) wavelet transform is used which is considered as lossless transform in the JPEG2000 standard. In the algorithm, (5, 3) Integer wavelet transformed high pass coefficients are difference expanded instead of Haar wavelet transformed coefficients in Mark Tian's algorithm. Based on the Algorithm developed for Matlab modeling, a new architecture for Reversible watermarking was designed and the hardware modeling for that architecture was done using Verilog HDL. By difference expanding the high pass coefficients of the image and embedding the watermark in those high pass coefficient, maximum embedding capacity over 90000 bits is achieved for a 256x256 image.

The Watermark embedding block is synthesized using Xilinx ISE and implemented on Spartan3 FPGA. The Reversible Watermarking Block operates at a maximum clock frequency of 62.073 MHz with a minimum period of 16.110ns. The Latency of the system is N+2 clock cycles for a total of N pixels macro block. The embedding capacity of 2bits at a time are used to embed in the high frequency coefficients, as number of bits to be embedded increases the Peak Signal to Noise Ratio decreases up to 31.3%.