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Compiling for reconfigurable computing: A survey

Published: 23 June 2010 Publication History

Abstract

Reconfigurable computing platforms offer the promise of substantially accelerating computations through the concurrent nature of hardware structures and the ability of these architectures for hardware customization. Effectively programming such reconfigurable architectures, however, is an extremely cumbersome and error-prone process, as it requires programmers to assume the role of hardware designers while mastering hardware description languages, thus limiting the acceptance and dissemination of this promising technology. To address this problem, researchers have developed numerous approaches at both the programming languages as well as the compilation levels, to offer high-level programming abstractions that would allow programmers to easily map applications to reconfigurable architectures. This survey describes the major research efforts on compilation techniques for reconfigurable computing architectures. The survey focuses on efforts that map computations written in imperative programming languages to reconfigurable architectures and identifies the main compilation and synthesis techniques used in this mapping.

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cover image ACM Computing Surveys
ACM Computing Surveys  Volume 42, Issue 4
June 2010
175 pages
ISSN:0360-0300
EISSN:1557-7341
DOI:10.1145/1749603
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Received: 01 November 2004
Published in CSUR Volume 42, Issue 4

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  1. Compilation
  2. FPGA
  3. custom-computing platforms
  4. hardware compilers
  5. high-level synthesis
  6. mapping methods
  7. reconfigurable computing

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