Marc Schlickling
ABSTRACT
Embedded systems are widely used for supporting our every day life. In the area of safety-critical systems human life often depends on the system's correct behavior. Many of such systems are hard real-time systems, so that the notion of correctness not only means functional correctness. They additionally have to obey stringent timing constraints, i.e. timely task completion under all circumstances is essential. An example for such a safety-critical system is the flight control computer in an airplane, which is responsible for stability, attitude and path control.
In order to derive guarantees on the timing behavior of hard real-time systems, the worst-case execution time (WCET) of each task in the system has to be determined. Saarland University and AbsInt GmbH have successfully developed the aiT WCET analyzer for computing safe upper bounds on the WCET of a task. The computation is mainly based on abstract interpretation of timing models of the processor and its periphery. Such timing models are currently hand-crafted by human experts. Therefore their implementation is a time-consuming and error-prone process.
Modern processors or system controllers are automatically synthesized out of formal hardware specifications like VHDL or Verilog. Besides the system' functional behavior, such specifications provide all information needed for the creation of a timing model. But due to their size and complexity, manually examining the sources is even more complex than only looking at the processor manuals. Moreover, this would not reduce the effort nor the probability of implementation errors.
To face this problem, this paper proposes a method for semi-automatically deriving suitable timing models out of formal hardware specifications in VHDL that fit to the tool chain of the aiT WCET analyzer. By this, we reduce the creation time of timing models from months to weeks.
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Index Terms
- Semi-automatic derivation of timing models for WCET analysis
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Reviews
Festus Gail Gray
Schlickling and Pister propose, in this paper, a method for deriving timing models using the information in formal very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) specifications, in a semi-automatic way. The first step (model preprocessing), which should be able to be fully automated, reduces the overall size of the VHDL model by eliminating parts that are not relevant for timing behavior. The authors claim that the second step (processor state abstraction) will always require human intervention. The proposed algorithm is iterative in nature, involving repeated applications of the two steps described. The final result of the iterative process is a timing model from which C++ simulation code can be generated. All possible paths in the resulting execution tree are simulated to obtain upper bounds on the worst-case execution times (WCET) for each critical system task. Since the implementation of the outlined sequence of model analyses and transformations was still under development at the time the conference paper was presented, the authors were unable to give any reasonable experimental results and were unable to compare the semi-automatic method to a manually derived timing model. One drawback to the method is that "abstract interpretation of the timing model is guaranteed to give upper WCET bounds [...] relative to the [timing] model itself. If the [timing] model fails to correctly describe the system's behavior, the computed WCET bound may be incorrect" [1]. Since the extracted timing information comes from formal VHDL specifications that include timing information, this could guarantee correct timing models. As ongoing work, the authors will try to prove that the resulting model, after the application of their transformations and state abstractions, correctly approximates the timing behavior of the original system. The stated goals are certainly laudable, but clearly much work remains to be done. It is not clear how much of the proposed implementation, if any, could be applied to other hardware description languages. Online Computing Reviews Service
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