ABSTRACT
For memory constrained embedded systems code size is at least as important as performance. One way of increasing code density is to exploit compact instruction formats, e.g. ARM Thumb, where the processor either operates in standard or compact instruction mode. The ARCompact ISA considered in this paper is different in that it allows freeform mixing of 16- and 32-bit instructions without a mode switch. Compact 16-bit instructions can be used anywhere in the code given that additional register constraints are satisfied. In this paper we present an integrated instruction selection and register allocation methodology and develop two approaches for mixed-mode code generation: a simple opportunistic scheme and a more advanced feedback-guided instruction selection scheme. We have implemented a code generator targeting the ARCompact ISA and evaluated its effectiveness against the ARC750D embedded processor and the EEMBC benchmark suite. On average, we achieve a code size reduction of 16.7% across all benchmarks whilst at the same time improving performance by on average 17.7%.
- ACE Associated Computer Experts bv. CoSy compiler development system. http://www.ace.nl, retrieved 12 August 2009.Google Scholar
- \textscArc International. Arc750D Core. http://www.arc.com, retrieved 12 August 2009.Google Scholar
- \textscArm Ltd. Arm Cortex-M3. http://www.arm.com, retrieved 12 August 2009.Google Scholar
- Árpád Beszédes, Rudolf Ferenc, Tibor Gyimóthy, André Dolenc, and Karsisto, Konsta. Survey of code-size reduction methods. ACM Computing Surveys, Vol. 35, No. 3, pp. 223--267, 2003. Google ScholarDigital Library
- John Bunda, Don Fussell, W.C. Athas, and Roy Jenevein. 16-bit vs. 32-bit instructions for pipelined microprocessors. SIGARCH Computer Architecture News, Vol. 21, No. 2, pp. 237--246, 1993. Google ScholarDigital Library
- http://electronicdesign.com/Articles/Index.cfm?ArticleID=5267 Dave Bursky. Nonvolatile Memory: More Than A Flash In The Pan. In electronic design, http://electronicdesign.com, ED Online ID 5267, July 2003.Google Scholar
- The Embedded Microprocessor Benchmark Consortium. Eembc Benchmark Suite. http://www.eembc.org, retrieved 12 August 2009.Google Scholar
- Richard A. Fuhler, Thomas J. Pennello, Michael Lee Jalkut, and Peter Warnes. Method and Apparatus for Compiling Instructions for a Data Processor. United States Patent US 7278137B1, Oct. 2, 2007.Google Scholar
- http://portal.acm.org/citation.cfm?id=882452.874375 A. Halambi, A. Shrivastava, P. Biswas, N. Dutt, A. Nicolau. An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE), p. 402, 2002. Google ScholarDigital Library
- Arvind Krishnaswamy and Rajiv Gupta. http://portal.acm.org/citation.cfm?id=859697 Profile guided selection of Arm and Thumb instructions. ACM SIGPLAN Notices, Vol. 32, No. 7, pp. 56--64, 2002. Google ScholarDigital Library
- Arvind Krishnaswamy and Rajiv Gupta. Mixed-width instruction sets. Communications of the ACM, Vol. 46, No. 8, pp. 47--52, 2003. Google ScholarDigital Library
- http://portal.acm.org/citation.cfm?id=1234677 Sheayun Lee, Jaejin Lee, Chang Park, Sang Min. Selective code transformation for dual instruction set processors. ACM Transactions on Embedded Computing Systems, Vol. 6, No. 2, 2007. Google ScholarDigital Library
- Mips Technologies. microMips Instruction Set Architecture. MD00690, Revision 01.00, October 2009.Google Scholar
- Richard Phelan. Improving Arm Code Density and Performance -- New Thumb Extensions to the Arm Architecture. Arm Thumb-2 Core Technology Whitepaper, June 2003.Google Scholar
- Jim Turley. Code compression under the microscope. In Embedded Systems Design, http://www.embedded.com, retrieved 12 August 2009.Google Scholar
- Liu Xianhua, Zhang Jiyu, Cheng Xu. http://portal.acm.org/citation.cfm?id=1244154 Efficient code size reduction without performance loss. In Proceedings of the ACM Symposium on Applied Computing (SAC), pp. 666--672, 2007. Google ScholarDigital Library
Index Terms
- Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions
Recommendations
Enhancing the performance of 16-bit code using augmenting instructions
Special Issue: Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool support for embedded systems (San Diego, CA).In the embedded domain, memory usage and energy consumption are critical constraints. Dual width instruction set embedded processors such as the ARM provide a 16-bit instruction set in addition to the 32-bit instruction set to address these concerns. ...
Enhancing the performance of 16-bit code using augmenting instructions
LCTES '03: Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systemsIn the embedded domain, memory usage and energy consumption are critical constraints. Dual width instruction set embedded processors such as the ARM provide a 16-bit instruction set in addition to the 32-bit instruction set to address these concerns. ...
Dynamic coalescing for 16-bit instructions
In the embedded domain, memory usage and energy consumption are critical constraints.Embedded processors such as the ARM and MIPS provide a 16-bit instruction set, (called Thumb in the case of the ARM family of processors), in addition to the 32-bit ...
Comments