research-article

Parameterized tiling revisited

Authors:

Muthu Manikandan Baskaran,

Albert Hartono,

Sanket Tavarageri,

Thomas Henretty,

P. SadayappanAuthors Info & Claims

CGO '10: Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization

Pages 200 - 209

https://doi.org/10.1145/1772954.1772983

Published: 24 April 2010 Publication History

Abstract

Tiling, a key transformation for optimizing programs, has been widely studied in literature. Parameterized tiled code is important for auto-tuning systems since they often execute a large number of runs with dynamically varied tile sizes. Previous work on tiled code generation has addressed parameterized tiling for the sequential context, and the parallel case with fixed compile-time constants for tile sizes. In this paper, we revisit the problem of generating tiled code using parametric tile sizes. We develop a systematic approach to formulate tiling transformations through manipulation of linear inequalities and develop a novel approach to overcoming the fundamental obstacle faced by previous approaches regarding generation of parallel parameterized tiled code. To the best of our knowledge, the approach proposed in this paper is the first compile-time solution to the problem of parallel parameterized code generation for affine imperfectly nested loops. Experimental results demonstrate the effectiveness of the implemented system.

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Cited By

Palkowski MGruzewski M(2023)Time and Energy Benefits of Using Automatic Optimization Compilers for NPDP TasksElectronics10.3390/electronics1217357912:17(3579)Online publication date: 24-Aug-2023
https://doi.org/10.3390/electronics12173579
Kelefouras VDjemame KKeramidas GVoros N(2022)A Methodology for Efficient Tile Size Selection for Affine Loop KernelsInternational Journal of Parallel Programming10.1007/s10766-022-00734-550:3-4(405-432)Online publication date: 23-May-2022
https://doi.org/10.1007/s10766-022-00734-5
Kelefouras VDjemame KKeramidas GVoros N(2022)An Analytical Model for Loop Tiling TransformationEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-031-04580-6_7(95-107)Online publication date: 27-Apr-2022
https://doi.org/10.1007/978-3-031-04580-6_7
Show More Cited By

Index Terms

Parameterized tiling revisited
1. Software and its engineering
  1. Software notations and tools
    1. Compilers
      1. Source code generation

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cover image ACM Conferences

CGO '10: Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization

April 2010

300 pages

ISBN:9781605586359

DOI:10.1145/1772954

General Chairs:
Andreas Moshovos
University of Toronto
,
Greg Steffan
University of Toronto
,
Program Chairs:
Kim Hazelwood
University of Virginia
,
David Kaeli
Northeastern University

Copyright © 2010 ACM.

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Published: 24 April 2010

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CGO '10

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CGO '10: 8th Annual IEEE/ ACM International Symposium on Code Generation and Optimization

April 24 - 28, 2010

Ontario, Toronto, Canada

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Overall Acceptance Rate 312 of 1,061 submissions, 29%

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Cited By

Palkowski MGruzewski M(2023)Time and Energy Benefits of Using Automatic Optimization Compilers for NPDP TasksElectronics10.3390/electronics1217357912:17(3579)Online publication date: 24-Aug-2023
https://doi.org/10.3390/electronics12173579
Kelefouras VDjemame KKeramidas GVoros N(2022)A Methodology for Efficient Tile Size Selection for Affine Loop KernelsInternational Journal of Parallel Programming10.1007/s10766-022-00734-550:3-4(405-432)Online publication date: 23-May-2022
https://doi.org/10.1007/s10766-022-00734-5
Kelefouras VDjemame KKeramidas GVoros N(2022)An Analytical Model for Loop Tiling TransformationEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-031-04580-6_7(95-107)Online publication date: 27-Apr-2022
https://doi.org/10.1007/978-3-031-04580-6_7
Abdelaal KKong MZhou HMoreira JMueller FEtsion Y(2021)Tile size selection of affine programs for GPGPUs using polyhedral cross-compilationProceedings of the 35th ACM International Conference on Supercomputing10.1145/3447818.3460369(13-26)Online publication date: 3-Jun-2021
https://dl.acm.org/doi/10.1145/3447818.3460369
Tavarageri SHeinecke AAvancha SKaul BGoyal GUpadrasta R(2021)PolyDLACM Transactions on Architecture and Code Optimization10.1145/343310318:1(1-27)Online publication date: 7-Jan-2021
https://dl.acm.org/doi/10.1145/3433103
Iooss GAlias CRajopadhye S(2021)Monoparametric Tiling of Polyhedral ProgramsInternational Journal of Parallel Programming10.1007/s10766-021-00694-2Online publication date: 18-Mar-2021
https://doi.org/10.1007/s10766-021-00694-2
Javanmard MAhmad ZKong MPouchet LChowdhury RHarrison RMars JTang LXue JWu P(2020)Deriving parametric multi-way recursive divide-and-conquer dynamic programming algorithms using polyhedral compilersProceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization10.1145/3368826.3377916(317-329)Online publication date: 22-Feb-2020
https://dl.acm.org/doi/10.1145/3368826.3377916
Mahdi Javanmard MAhmad ZZola JPouchet LChowdhury RHarrison R(2020)Efficient Execution of Dynamic Programming Algorithms on Apache Spark2020 IEEE International Conference on Cluster Computing (CLUSTER)10.1109/CLUSTER49012.2020.00044(337-348)Online publication date: Sep-2020
https://doi.org/10.1109/CLUSTER49012.2020.00044
Tillet PKung HCox DMattson TMuzahid ASolar-Lezama A(2019)Triton: an intermediate language and compiler for tiled neural network computationsProceedings of the 3rd ACM SIGPLAN International Workshop on Machine Learning and Programming Languages10.1145/3315508.3329973(10-19)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3315508.3329973
Zhao JCui HZhang YXue JFeng X(2018)Revisiting Loop Tiling for DatacentersProceedings of the 2018 International Conference on Supercomputing10.1145/3205289.3205306(328-340)Online publication date: 12-Jun-2018
https://dl.acm.org/doi/10.1145/3205289.3205306
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