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Via configurable three-input lookup-tables for structured ASICs

Published: 16 May 2010 Publication History

Abstract

In this article we study layout and circuit implementations of 3-input lookup table (3-LUT) for via configurable structured ASIC. We present a new 3-LUT circuit and several layout designs. We also propose a method to improve the delay of any logic function with fewer inputs. A 3-LUT, being able to realize all the 256 3-input functions, enables us to synthesize a circuit using both a standard cell synthesizer and an FPGA technology mapper such as FlowMap. Our study shows that circuits synthesized using a standard-cell synthesizer usually achieves better timing than that obtained by FlowMap. Our study further shows that the well-known 3-LUT implemented with multiplexers achieves better timing, area, and power dissipation. Our methodology can be also employed to study look-up tables with more inputs.

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Cited By

View all
  • (2013)Architecture and design flow for a highly efficient structured ASICIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.219047821:3(424-433)Online publication date: 1-Mar-2013
  • (2012)Improved Via-Programmable Structured ASIC VPEX3 and Its EvaluationIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E95.A.1518E95.A:9(1518-1528)Online publication date: 2012
  • (2012)Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flowIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.217071220:12(2184-2197)Online publication date: 1-Dec-2012

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    cover image ACM Conferences
    GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI
    May 2010
    502 pages
    ISBN:9781450300124
    DOI:10.1145/1785481
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 16 May 2010

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    Author Tags

    1. layout
    2. look-up-table
    3. structured ASIC
    4. via-configurable
    5. vlsi

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    May 16 - 18, 2010
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    View all
    • (2013)Architecture and design flow for a highly efficient structured ASICIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.219047821:3(424-433)Online publication date: 1-Mar-2013
    • (2012)Improved Via-Programmable Structured ASIC VPEX3 and Its EvaluationIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E95.A.1518E95.A:9(1518-1528)Online publication date: 2012
    • (2012)Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flowIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.217071220:12(2184-2197)Online publication date: 1-Dec-2012

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