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View all- Ho MAi YChau TYuen SChoy CLeong PPun K(2013)Architecture and design flow for a highly efficient structured ASICIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.219047821:3(424-433)Online publication date: 1-Mar-2013
- HORI RKITAMORI TUEOKA TYOSHIKAWA MFUJINO T(2012)Improved Via-Programmable Structured ASIC VPEX3 and Its EvaluationIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E95.A.1518E95.A:9(1518-1528)Online publication date: 2012
- Tung HLin RLi MHeish T(2012)Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flowIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.217071220:12(2184-2197)Online publication date: 1-Dec-2012