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A mask double patterning technique using litho simulation by wavelet transform

Published: 16 May 2010 Publication History

Abstract

Optical Lithography is a key to semiconductor device scaling. As technology continues to scale, the fundamental limits of lithography are pushed to an extreme. Today 193nm light is used to print features in 45nm technology node. As the minimum feature size on the mask is less than half the wavelength of light used for the lithography process, diffraction at the mask edges dominates the errors in mask printing. Mask transfer fidelity issues are countered using a number of Resolution Enhancement Techniques (RET) which include Optical Proximity Correction (OPC), Phase Shift Masking (PSM), Sub Resolution Assist Features (SRAF) and Dual Patterning Lithography (DPL). DPL reduces wafer throughput but has become a necessity in current and upcoming technology nodes. It involves splitting patterns in a mask into two masks that are exposed separately. DPL CAD problem is a pattern coloring problem to minimize mask edge placement error (EPE). EPE results from interaction of near field waves and any geometric solution that does not consider interaction of fields, suffers from inaccuracies. Previous publications were mostly focused on a rule based geometric solution. In this paper we investigate a method to implement DPL using fast lithography simulation taking into account not only the bad, but also the beneficial effects of having polygons in the mask close to one another in the final partitioned layout. We present results on metal layer 2 of the ISCAS-85 benchmarks. Results show that even though our model based solution is slower, unlike many previous approaches, the final output meets the objectives of reducing EPE.

References

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Kahng, A. B. and Pati, Y. C. 1999. Subwavelength optical lithography: challenges and impact on physical design. In Proceedings of the 1999 international Symposium on Physical Design (Monterey, California, United States, April 12 -- 14, 1999). ISPD '99. ACM, New York, NY, 112--119.
[2]
Liebmann, L. W. 2003. Layout impact of resolution enhancement techniques: impediment or opportunity?. In Proceedings of the 2003 international Symposium on Physical Design (Monterey, CA, USA, April 06 -- 09, 2003). ISPD '03. ACM, New York, NY, 110--117.
[3]
Micrea Dusa, Jo Finders, and Stephen Hsu. Double patterning lithography: The bridge between low k1 arf and euv. In Microlithography World, Feb 2008.
[4]
Kahng, A.B.; Park, C.-H.; Xu, X.; Hailong Yao, "Layout decomposition for double patterning lithography," Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on Computer aided design, vol., no., pp.465--472, 10--13 Nov. 2008.
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Yuan, K., Yang, J., and Pan, D. 2009. Double patterning layout decomposition for simultaneous conflict and stitch minimization. In Proceedings of the 2009 international Symposium on Physical Design (San Diego, California, USA, March 29 -- April 01, 2009). ISPD '09. ACM, New York, NY, 107--114.
[6]
Split and design guidelines for double patterning. Vincent Wiaux, Staf Verhaegen, Shaunee Cheng, Fumio Iwamoto, Patrick Jaenen, Mireille Maenhoudt, Takashi Matsuda, Sergei Postnikov, and Geert Vandenberghe, Proc. SPIE 6924, 692409 (2008),
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Double pattern EDA solutions for 32nm HP and beyond George E. Bailey, Alexander Tritchkov, Jea-Woo Park, Le Hong, Vincent Wiaux, Eric Hendrickx, Staf Verhaegen, Peng Xie, and Janko Versluijs, Proc. SPIE 6521, 65211K (2007)
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Issues and challenges of double patterning lithography in DRAM Seo-Min Kim, Sun-Young Koo, Jae-Seung Choi, Young-Sun Hwang, Jung-Woo Park, Eung-Kil Kang, Chang-Moon Lim, Seung-Chan Moon, and Jin-Woong Kim, Proc. SPIE 6520, 65200H (2007)
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Revisiting the layout decomposition problem for double patterning lithography Andrew B. Kahng, Chul-Hong Park, Xu Xu, and Hailong Yao, Proc. SPIE 7122, 71220N (2008)
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Double patterning design split implementation and validation for the 32nm node Martin Drapeau, Vincent Wiaux, Eric Hendrickx, Staf Verhaegen, and Takahiro Machida, Proc. SPIE 6521, 652109 (2007).
[11]
Development of layout split algorithms and printability evaluation for double patterning technology Tsann-Bim Chiou, Robert Socha, Hong Chen, Luoqi Chen, Stephen Hsu, Peter Nikolsky, Anton van Oosten, and Alek C. Chen, Proc. SPIE 6924, 69243M (2008),
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Rodrigues, R., Sreedhar, A., and Kundu, S. Optical Lithography Simulation using Wavelet Transform. In Proceedings of the XXVII International Conference on Computer Design (Lake Tahoe, California, USA, October 4 -- 7, 2009). ICCD '09

Cited By

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  • (2011)Model based double patterning lithography (DPL) and simulated annealing (SA)2011 12th International Symposium on Quality Electronic Design10.1109/ISQED.2011.5770754(1-8)Online publication date: Mar-2011

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cover image ACM Conferences
GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI
May 2010
502 pages
ISBN:9781450300124
DOI:10.1145/1785481
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 16 May 2010

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Author Tags

  1. double patterning lithography
  2. edge placement error
  3. polygon stitch
  4. wavelet transform

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GLSVLSI '10: Great Lakes Symposium on VLSI 2010
May 16 - 18, 2010
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  • (2011)Model based double patterning lithography (DPL) and simulated annealing (SA)2011 12th International Symposium on Quality Electronic Design10.1109/ISQED.2011.5770754(1-8)Online publication date: Mar-2011

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