ABSTRACT
For timing-driven or yield-driven designs, non-tree routing has become more and more popular and additional loops provide the redundant paths to protect against the effect of the open defects. Based on the assumption of a single wiring open in a signal net, it is known that the non-tree interconnection of a signal net has no adjacent loop. In this paper, based on the concept of splitting a time-equivalent node or edge in a cyclic connection for timing analysis, a 0-1 integer linear programming(ILP) formulation for resource-constrained timing-driven link insertion is proposed to insert timing-driven links to maximize the reduced delay of the critical path in a rectilinear Steiner tree under a given resource constraint. The experimental results show that our proposed algorithm has the 21.0% and 23.5% reduction of the critical delay on the average for the tested trees in reasonable CPU time under the 10% and 20% resource constraint of the total wirelength, respectively.
- B. A. McCoy and G. Robins, "Non-tree routing," IEEE Trans. on CAD of Integrated Circuits and Systems, Vol.14, no.6, pp., 1995.Google Scholar
- T. Xue and E. S. Kuh, "Post routing performance optimization via tapered link insertion and wiresizing," Design, Automation and Test in Europe, pp.74--79, 1995. Google ScholarDigital Library
- S. Hu, Q. Li, J. Hu and P. Li, "Utilizing redundancy for timing critical interconnect," IEEE Transactions on VLSI Systems, vol. 15, no. 10, pp.1067--1080, 2007. Google ScholarDigital Library
- A. B. Kahng, B. Liu, and I. I. Mandoiu, "Non-tree routing for reliability and yield improvement," IEEE International Conference on Computer-Aided Design, pp.260--266, 2002. Google ScholarDigital Library
- J. Bickford, M. Buehler, et.al., "Yield improvement by local wiring redundancy," International Symposium on Quality ED, pp.473--478, 2006. Google ScholarDigital Library
- P. Panitz, M. Olbrich, J. Koehl, and E. Barke, "Robust wiring networks for DfY considering timing constraints," ACM Great Lakes Symposium on VLSI, pp.43--48, 2007. Google ScholarDigital Library
- P. Panitz, M. Olbrich, E. Barke, M. Buehler and J. Koehl, "Considering possible opens in non-tree topology wire delay calculation," ACM Great Lakes Symposium on VLSI, pp.17--22, 2008. Google ScholarDigital Library
- J. T. Yan and Z. W. Chen, "Reliability-driven redundant wire insertion for yield improvement," ACM Great Lakes Symposium on VLSI, pp.409--412, 2009. Google ScholarDigital Library
- Z. W. Chen and J. T. Yan, "Optimal transformation of non-tree interconnects for timing analysis," The 1st Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics, pp.69--72, 2009.Google Scholar
- lp_solve: an open source linear programming solver. {Online}. Available: http://sourceforge.net/projects/lpsolveGoogle Scholar
Index Terms
- Resource-constrained timing-driven link insertion for critical delay reduction
Recommendations
Resource-constrained link insertion for delay reduction
Under the design experience of a single open on any wiring segment in a signal net, it is known that the non-tree topology for a signal net does not need any adjacent loop. In this paper, based on two time-equivalent splitting operations in a cyclic ...
Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization
VLSID '07: Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded SystemsIn this paper, given a full-chip routing result with a set of rectilinear Steiner trees, based on the computation of critical areas for short and open wires, a two-phase timingconstrained yield-driven approach is proposed to minimize the critical area ...
Comments