Suman K. Mandal
Saraju P. Mohanty
ABSTRACT
Network-on-Chip (NoC) is an on-chip communication solution in the future system-on-a-chip (SoC) necessitating high performance operation with low power dissipation. We present a novel dynamic power management technique for low power NoC router buffers using nano CMOS SRAMS. A feedback controller was designed for block level power management and a power aware adaptive controller was designed for low power flit storage encoding to reduce energy consumptions in the router buffers. Experiments with the proposed scheme showed up to 20% reduction in energy consumption while improving throughput by up to 21%.
- Simunic, T., Boyd, S., "Managing power consumption in networks on chips," Design, Automation and Test in Europe Conference and Exhibition, pp.110--116, 2002. Google Scholar
Digital Library
- Jun Wang; Hongbo Zeng; Kun Huang; Ge Zhang; Yan Tang, "Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor," Design, Automation and Test in Europe, pp.792--795, 2008. Google ScholarDigital Library
- Banerjee, A., Mullins, R., and Moore, S. "A Power and Energy Exploration of Network-on-Chip Architectures", In Proceedings of the First international Symposium on Networks-on-Chip, pp. 163--172, 2007. Google ScholarDigital Library
- Young Hoon Kang; Taek-Jun Kwon; Draper, J., "Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers," ACM/IEEE International Symposium on Networks-on-Chip, pp.250--255, 2009. Google ScholarDigital Library
- Wang, L., Zhang, J., Yang, X., and Wen, D., "Router with centralized buffer for network-on-chip". In Proceedings of the 19th ACM Great Lakes Symposium on VLSI, pp. 469--474, 2009. Google ScholarDigital Library
- Ogras, U. Y., Hu, J., and Marculescu, R., "Key research problems in NoC design: a holistic perspective.", In Proceedings of the 3rd IEEE/ACM/IFIP international Conference on Hardware/Software Codesign and System Synthesis, pp. 69--74, 2005. Google ScholarDigital Library
- Chrysostomos A. Nicopoulos, Dongkook Park, Jongman Kim, N. Vijaykrishnan, Mazin S. Yousif, Chita R. Das, "ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers," IEEE/ACM International Symposium on Microarchitecture, pp. 333--346, 2006. Google ScholarDigital Library
- Shim, K. S., Cho, M. H., Kinsy, M., Wen, T., Lis, M., Suh, G. E., and Devadas, S. 2009. Static virtual channel allocation in oblivious routing. In Proceedings of the 2009 3rd ACM/IEEE international Symposium on Networks-on-Chip, pp. 38--43, 2009. Google ScholarDigital Library
- Kodi, A., Sarathy, A., and Louri, A., Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture. In Proceedings of the 3rd ACM/IEEE Symposium on Architecture For Networking and Communications Systems, pp. 47--56, 2007. Google ScholarDigital Library
- Koranne, S., "Element Interconnect Bus", Practical Computing on the Cell Broadband Engine, Springer US, pp. 61--66, 2009 (ISBN: 978-1-4419-0342-6).Google Scholar
- Lee, C., Potkonjak, M., and Mangione-Smith, W. H. 1997. MediaBench: a tool for evaluating and synthesizing multimedia and communications systems. In Proceedings of the 30th Annual ACM/IEEE international Symposium on Microarchitecture, pp. 330--335, 1997. Google ScholarDigital Library
- M.R. Guthaus, J.S. Ringenberg, D. Ernst, T.M. Austin, T. Mudge, R.B. Brown, "MiBench: A free, commercially representative embedded benchmark suite," Annual IEEE International Workshop Workload Characterization, pp. 3--14, 2001. Google ScholarDigital Library
- The SPEC2006 Benchmarks, http://www.spec.org.Google Scholar
- Kodi, A., Sarathy, A., and Louri, A., Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture. In Proceedings of the 3rd ACM/IEEE Symposium on Architecture For Networking and Communications Systems, pp. 47--56, 2007. Google ScholarDigital Library
- W. Zhao and Y. Cao. New Generation of Predictive Technology Model for sub-45nm Design Exploration. In Proceedings of International Symposium on Quality Electronic Design, pp. 585--590, 2006. Google ScholarDigital Library
- http://archc.sourceforge.net.Google Scholar
- S. K. Mandal, N. Gupta, A. Mandal, J. Malave, J. D. Lee and R. Mahapatra, "NoCBench: A Benchmarking Platform for Network on Chip", In Proc. of Workshop on Unique Chips and Systems, 2009.Google Scholar
- G. Thakral, S. P. Mohanty, D. Ghai, and D. K. Pradhan, "A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM", in Proceedings of the 23rd IEEE International Conference on VLSI Design, pp. 45--50, 2010. Google ScholarDigital Library
Index Terms
- Low power nanoscale buffer management for network on chip routers
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