ABSTRACT
Next generation system designs are challenged by multiple "walls": among them, the inter-related impediments offered by power dissipation limits and reliability are particularly difficult ones that all current chip/system design teams are grappling with. In this paper, we first describe the attendant challenges in integrated (multi-dimensional) pre-silicon modeling and the solution approaches being pursued. Later, we focus on leading edge solutions for power, thermal and failure-rate mitigation that have been proposed in our R&D work over the past decade.
- Brooks, D., Bose, P., Schuster, S., Jacobson, H., Kudva, P., Buyuktosunoglu, A., Wellman, J--D., Zyuban, V., Gupta, M. and Cook, P. 2000. Power-aware microarchitecture: design and modeling challenges for the next generation microprocessors. IEEE Micro, 20, 6, (Nov/Dec 2000). Google ScholarDigital Library
- Borkar, S. 2005. Designing reliable systems from unreliable components: the challenges of transistor variability and degradation. IEEE Micro, 25, 6, (Nov. 2005). Google ScholarDigital Library
- Albonesi, D., Balasubramonian, R., Dropsho, S., Dwarkadas, S., Friedman, E., Huang, M., Kursun, V., Magklis, G., Scott, M., Semeraro, G., Bose, P., Buyuktosunoglu, A., Cook, P. and Schuster, S. 2003. Dynamically tuning processor resources with adaptive processing. IEEE Computer, 36, 12, (2003), 43--51. Google ScholarDigital Library
- R. Singhal. 2008. Inside IntelR CoreTM Microarchitecture (Nehalem). In Digest of the Hot Chips conference, (August 2008).Google Scholar
- Brooks, D., Tiwari, V. and Martonosi, M. 2000. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th International Symposium on Computer Architecture, ISCA-27, (June 2000). Google ScholarDigital Library
- Brooks, D., Bose, P., Srinivasan, V., Gschwind, M., Emma, P., Rosenfield, M. 2003. New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors. IBM Journ. of Res. And Develop., 47, 5/6, (2003). Google ScholarDigital Library
- Jiang, L., Kolluri, S., Rubin, B., Smith, H., Colgan, E., Scheuermann, M., Wakil, J., Deutch, A., Gill, J. 2008. Thermal modeling of on-chip interconnects and 3D packaging using EM tools. In Proceedings of IEEE Electrical Performance of Electronic Packaging (EPEP), (October 2008).Google ScholarCross Ref
- Skadron, K., Stan, M., Sankaranarayanan, K., Huang, W., Velusamy, S. and Tarjan, D. 2004. Temperature-aware microarchitecture: modeling and implementation. ACM Transactions on Architecture and Code Optimization, 1, 1, (March 2004), 94--125. Google ScholarDigital Library
- Hamann, H., Lacey, J., Weger, A., Bose, P., Hu, Z., Cohen, E., Wakil, J. 2007. Hotspot-limited microprocessors: direct temperature and power distribution measurements. Journal of Solid State Circuits, JSSC, 42, 1, (January 2007).Google Scholar
- Thermal Analysis Solvers from ANSYS: http://www.ansys.com .Google Scholar
- Zyuban, V., Brooks, D., Srinivasan, V., Gschwind, M., Bose, P., Strenski, P. and Emma, P. 2004. Integrated analysis of power and performance of pipelined microprocessors. IEEE Transactions on Computers, 53, 8, (August 2004). Google ScholarDigital Library
- Li, Y., Brooks, D., Hu, Z. and Skadron, K. 2005. Performance, energy, and thermal considerations for SMT and CMP architectures. 2005. In Proceedings of the 11th International Symposium on High-Performance Computer Architecture, HPCA-11, (Feb. 2005). Google ScholarDigital Library
- Zyuban, V. and Strenski, P. 2002. Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels. In Proceeedings of the International Symposium on Low Power Electronics and Design, ISLPED, (August 2002), 166--171. Google ScholarDigital Library
- Rivers, J. and Kudva, P. 2009. Reliability challenges and system performance at the architecture level. IEEE Design & Test of Computers, 26, 6, (2009), 62--73. Google ScholarDigital Library
- Mukherjee, S., Emer, J. and Reinhardt, S. 2005. The soft error problem: an architectural perspective. In Proceedings of the 11th International Symposium on High Performance Computer Architecture, HPCA-11, (February 2005). Google ScholarDigital Library
- Li, X., Adve, S., Bose, P., Rivers, J. 2005. SoftArch: an architecture-level tool for modeling and analyzing soft errors. In Proceedings of the International Conference on Dependable Systems and Networks, DSN), (June 2005). Google ScholarDigital Library
- Li, X., Adve, S., Bose, P. and Rivers, J. 2007. Architecture-level soft error analysis: examining the limits of common assumptions. In Proceedings of the International Conference on Dependable Systems and Networks, DSN, (June 2007). Google ScholarDigital Library
- Rivers, J., Bose, P., Kudva, P., Wellman, J-D., Sanda, P., Cannon, E. and Alves, L. 2008. Phaser: Phased methodology for modeling the system-level effects of soft errors. IBM Journal of Research and Development, 52, 3, (2008), 293--306. Google ScholarDigital Library
- Wang, N., Quek, J., Rafacz, T. and Patel, S. 2004. Characterizing the effects of transient faults on a high-performance processor pipeline. In Proceedings of the International Conference on Dependable Systems and Networks, DSN, (June 2004), 61--70. Google ScholarDigital Library
- Ramachandran, P., Kudva, P., Kellington, J., Schumann, J. and Sanda, P. 2008. Statistical Fault Injection. In Proceedings of the International Conference on Dependable Systems and Networks, DSN (June 2008), 122--127.Google Scholar
- Sanda, P., Kellington, J., Kudva, P., Kalla, R., McBeth, R., Ackaret, J., Lockwood, R., Schumann, J. and Jones, C. 2008. Soft-error resilience of the IBM POWER6 processor. IBM Journal of Research and Development, 52, 3, (2008), 275--284. Google ScholarDigital Library
- Reddi, V., Gupta, M., Holloway, G., Smith, M.,Wei, G-Y. and Brooks, D. 2009. Voltage emergency prediction: a signature-based approach to reducing voltage emergencies. In Proceedings of the 15th International Symposium on High-Performance Computer Architecture, HPCA--15, (February 2009).Google Scholar
- Gupta, M., Rivers, J., Bose, P., Wei, G-Y. and Brooks, D. 2009. Tribeca: design for PVT variations with local recovery and fine-grained adaptation. In Proceedings of the 42nd Annual International Symposium on Microarchitecture, Micro-42, (Dec. 2009). Google ScholarDigital Library
- Srinivasan, J., Adve, S., Bose, P and Rivers, J. 2004. The impact of technology scaling on lifetime reliability. In Proceedings of the International Conference on Dependable Systems and Networks, DSN, (June 2004). Google ScholarDigital Library
- Shin, J., Zyuban, V., Hu, Z., Rivers, J and Bose, P. 2007. A framework for architecture-level lifetime reliability modeling. In Proceedings of the International Conference on Dependable Systems and Networks, DSN, (June 2007). Google ScholarDigital Library
- Isci, C., Buyuktosunoglu, A., Bose, P. and Martonosi, M. 2006. An analysis of efficient multi-core global power management policies: maximizing performance for a given power budget. In Proceedings of the 39th Annual International Symposium on Microarchitecture, MICRO-39, (December 2006). Google ScholarDigital Library
- Bergamaschi, R., Han, G., Buyuktosunoglu, A., Nair, I., Janssen, G., Dittman, G., Dhanwada, N., Hu, Z., Bose, P. and Darringer, J. 2008. Exploring power management in multi-core systems. In Proceedings of Asia--Pacific Design Automation Conference, ASP-DAC, (January 2008). Google ScholarDigital Library
- Sharkey, J., Buyuktosunoglu, A. and Bose, P. 2007. Evaluating design tradeoffs in on-chip power management for CMPs. In Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED, (August 2007). Google ScholarDigital Library
- Hu, Z., Buyuktosunoglu, A., Srinivasan, V., Zyuban, V., Bose, P. and Jacobson, H. 2004. Microarchitectural techniques for power-gating of execution units. In Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED, (Aug. 2004). Google ScholarDigital Library
- Lungu, A., Bose, P., Buyuktosunoglu, A and Sorin, D. 2009. Dynamic power gating with quality guarantees. In Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED, (August 2009). Google ScholarDigital Library
- Buyuktosunoglu, A., Karkhanis, T., Albonesi, D. and Bose, P. 2003. Energy efficient co-adaptive instruction fetch and issue. In Proceedings of the International Symposium on Computer Architecture, ISCA, (June 2003). Google ScholarDigital Library
- Brooks, D. and Martonosi, M. 2001. Dynamic thermal management for high-performance microprocessors. In Proceedings of the 7th International Symposium on High-Performance Computer Architecture, HPCA-7, (January 2001). Google ScholarDigital Library
- Choi, J., Cher, C-Y., Franke, H., Hamann, H., Weger, A. and Bose, P. 2007. Thermal-aware task scheduling at the system software level. In Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED, (August, 2007). Google ScholarDigital Library
- Kursun, E. and Cher, C-Y. 2009. Temperature variation characterization and thermal management of multicore architectures, IEEE Micro, 29, 1, (2009), 116--126. Google ScholarDigital Library
- Srinivasan, J., Adve, S., Bose, P. and Rivers, J. 2004. The case for lifetime reliability-aware microprocessors. In Proceedings of the 31st International Symposium on Computer Architecture, ISCA-2004, (June 2004). Google ScholarDigital Library
- Srinivasan, J., Adve, S., Bose, P. and Rivers, J. 2005. Lifetime reliability: towards an architectural solution. IEEE Micro, 25, 3, (May-June 2005). Google ScholarDigital Library
- Shin, J., Zyuban, V., Bose, P. and Pinkston, T. 2008. A proactive wearout recovery approach of microarchitectural redundancy to extend cache SRAM lifetime. In Proceedings of the 35th International Symposium on Computer Architecture, ISCA-35, (June 2008). Google ScholarDigital Library
- Emma, P. and Kursun, E. 2009. Opportunities and challenges for 3D systems and their design. IEEE Design & Test of Computers, 26, 5, (2009), 6--14. Google ScholarDigital Library
Index Terms
- Power-efficient, reliable microprocessor architectures: modeling and design methods
Recommendations
Challenges in Low Power Microprocessor Design
VLSID '96: Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile CommunicationThis paper addresses the challenge of controlling power dissipation in the microprocessor domain. Power efficiency in microprocessors is achieved not as much by by low watts, but more by increaed SpecInt/Watt. With process and voltage gains often being ...
Interconnect-power dissipation in a microprocessor
SLIP '04: Proceedings of the 2004 international workshop on System level interconnect predictionInterconnect power is dynamic power dissipation due to switching of interconnection capacitances. This paper describes the characterization of interconnect power in a state-of-the-art high-performance microprocessor designed for power efficiency. The ...
Comments