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On-chip power supply noise and its implications on timing

Published: 16 May 2010 Publication History

Abstract

We address two problems of assessing the influence of power- supply variations on timing analysis. We present a method to assign a supply-dependent hold margin; and we describe a method to accurately characterize logic gates for the sen- sitivity of delay on supply-voltage variations. We use a com- mercial microcontroller as a design example.

References

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Raphael, 2006.03. Synopsys, CA., 2006.
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D. A. Andersson et al. Supply voltage drop study considering on-chip self inductance of a 32-bit processor's power grid. In International Workshop on Signal Propagation on Interconnects, 2009.
[3]
T. Enami et al. Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise. IEEE Transactions on Computer-Aided Design, 28(4), 2009.
[4]
H. S. Kim and D. M. H. Walker. Statistical static timing analysis considering the impact of power supply noise in VLSI circuits. In MTV '06: Proceedings of the Seventh International Workshop on Microprocessor Test and Verification, Washington, DC, USA, 2006.
[5]
S. Kirolos et al. Accurate analytical delay modeling of cmos clock buffers considering power supply variations. In Proc. of ISCAS, 2008.
[6]
L. Ljung. System Identification Toolbox for use with MATLAB. The Mathworks, 1997.
[7]
A. V. Mezhiba and E. G. Friedman. Power distribution networks in high speed integrated circuits. Kluwer, 2004.
[8]
M. Pude et al. An analytical propagation delay model with power supply noise effects. In International Symposium on Circuits and Systems, 2006.
[9]
M. Saint-Laurent and M. Swaminathan. Impact of power-supply noise on timing in high-frequency microprocessors. IEEE Transactions on Advanced Packaging, 27(1):135--144, 2004.

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    cover image ACM Conferences
    GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI
    May 2010
    502 pages
    ISBN:9781450300124
    DOI:10.1145/1785481
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 16 May 2010

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    Author Tags

    1. hold margins
    2. supply-voltage variations

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    GLSVLSI '10
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    GLSVLSI '10: Great Lakes Symposium on VLSI 2010
    May 16 - 18, 2010
    Rhode Island, Providence, USA

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    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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