research-article

Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design

Authors:

Ting-Chi WangAuthors Info & Claims

GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI

Pages 423 - 428

https://doi.org/10.1145/1785481.1785580

Published: 16 May 2010 Publication History

Abstract

In this paper, we study a floorplanning problem for die-stacking System-in-Package (SiP) design in which the wire bonding method is used to connect signals between different dies. We present an approach which sequentially determines a floorplan for each die such that the generated floorplan has minimal on-chip wirelength and satisfies given fixed-outline and temperature constraints. The experimental results indicate that our approach has 100% successful rate in producing a feasible floorplan for each test case.

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Cited By

Yi Zhao Khursheed SAl-Hashimi BZhiwen Zhao (2016)Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICs2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2016.7753572(1-6)Online publication date: Sep-2016
https://doi.org/10.1109/VLSI-SoC.2016.7753572

Index Terms

Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

cover image ACM Conferences

GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI

May 2010

502 pages

ISBN:9781450300124

DOI:10.1145/1785481

General Chairs:
R. Iris Bahar
Brown University, USA
,
Fabrizio Lombardi
Northeastern University, USA
,
Program Chairs:
David Atienza
EPFL, Switzerland
,
Erik Brunvand
University of Utah, USA

Copyright © 2010 ACM.

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New York, NY, United States

Publication History

Published: 16 May 2010

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GLSVLSI '10: Great Lakes Symposium on VLSI 2010

May 16 - 18, 2010

Rhode Island, Providence, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Yi Zhao Khursheed SAl-Hashimi BZhiwen Zhao (2016)Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICs2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2016.7753572(1-6)Online publication date: Sep-2016
https://doi.org/10.1109/VLSI-SoC.2016.7753572

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