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A high-speed AES architecture implementation

Published: 17 May 2010 Publication History

Abstract

We present in this paper a high performance implementation for the Advanced Encryption Standard (AES) standard. The design goal is directed toward efficient implementation of an AES cryptocore. The proposed architecture exhibits parallelism by concurrently processing all the bytes of a data block and computes each round key on-the-fly. The design implements both AES encryption and decryption by efficiently sharing the complex design modules. The proposed high-speed iterative implementation performing the AES operations in 11 clock cycles was synthesized for ALTERA's Cyclone II FPGA.

References

[1]
M. F. Elisabeth Oswald, Kerstin Lemke, Francois-Xavier Standaert, Thomas Wollinger, Johannes Wolkerstorfer: "State of the Art in Hardware Architectures", European Network of Excellence in Cryptology, 2005.
[2]
J. Daemen, and V. Rijmen, The Design of Rijndael: Springer-Verlag New York, Inc., 2002.
[3]
A. Hodjat, I. Verbauwhede: "Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors", Transactions on Computers, vol. 55, no. 4, pp. 366--372, 2006.
[4]
N. M. Kosaraju, M. Varanasi, S. P. Mohanty: "A high-performance VLSI architecture for advanced encryption standard (AES) algorithm", International Conference on VLSI Design, 2006.

Cited By

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  • (2013)A new lightweight and high performance AES S-box using modular design2013 IEEE International Conference on Circuits and Systems (ICCAS)10.1109/CircuitsAndSystems.2013.6671613(65-70)Online publication date: Sep-2013

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Published In

cover image ACM Conferences
CF '10: Proceedings of the 7th ACM international conference on Computing frontiers
May 2010
370 pages
ISBN:9781450300445
DOI:10.1145/1787275
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 May 2010

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Author Tags

  1. aes
  2. cryptochip
  3. fpga
  4. hardware
  5. optimization

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CF'10
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CF'10: Computing Frontiers Conference
May 17 - 19, 2010
Bertinoro, Italy

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CF '10 Paper Acceptance Rate 30 of 113 submissions, 27%;
Overall Acceptance Rate 273 of 785 submissions, 35%

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Cited By

View all
  • (2013)A new lightweight and high performance AES S-box using modular design2013 IEEE International Conference on Circuits and Systems (ICCAS)10.1109/CircuitsAndSystems.2013.6671613(65-70)Online publication date: Sep-2013

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