research-article

Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs

Authors:

Amir-Mohammad Rahmani,

Pasi Liljeberg,

Hannu TenhunenAuthors Info & Claims

CF '10: Proceedings of the 7th ACM international conference on Computing frontiers

Pages 267 - 276

https://doi.org/10.1145/1787275.1787335

Published: 17 May 2010 Publication History

Abstract

Distributing a single global clock across a chip while meeting the power requirements of the design is a troublesome task due to shrinking technology nodes associated with high clock frequencies. To deal with this, network-on-chip (NoC) architectures partitioned into several voltage-frequency islands (VFIs) have been proposed. To interface the islands on a chip, operating at different frequencies, a complex bi-synchronous FIFO design is inevitable. However, these FIFOs are not needed if adjacent switches belong to the same clock domain. In this paper, a Reconfigurable Synchronous/Bi-Synchronous (RSBS) FIFO is proposed which can adapt its operation to either synchronous or bi-synchronous mode. The FIFO is presented by three different scalable and synthesizable design styles and, in addition, some techniques are suggested to show how the FIFO could be utilized in a VFI-based NoC. Our analysis reveal that the RSBS FIFOs can help to achieve up to 15% savings in the average power consumption of NoC switches and 29% improvement in the total average packet latency in the case of MPEG-4 encoder application, when compared to a non-reconfigurable architecture.

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Cited By

Rahmani ALiljeberg PPlosila JTenhunen H(2013)Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channelsJournal of Computer and System Sciences10.1016/j.jcss.2012.09.00479:4(440-456)Online publication date: 1-Jun-2013
https://dl.acm.org/doi/10.1016/j.jcss.2012.09.004
Rahmani AVaddina KLiljeberg PPlosila JTenhunen H(2011)Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical ChannelsIntegrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation10.1007/978-3-642-24154-3_28(278-287)Online publication date: 2011
https://doi.org/10.1007/978-3-642-24154-3_28
Rahmani ALiljeberg PPlosila JTenhunen H(2010)An efficient VFI-based NoC architecture using Johnson-encoded Reconfigurable FIFOsNORCHIP 201010.1109/NORCHIP.2010.5669474(1-5)Online publication date: Nov-2010
https://doi.org/10.1109/NORCHIP.2010.5669474

Index Terms

Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs
1. Hardware

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cover image ACM Conferences

CF '10: Proceedings of the 7th ACM international conference on Computing frontiers

May 2010

370 pages

ISBN:9781450300445

DOI:10.1145/1787275

General Chair:
Nancy M. Amato
Texas A&M University, USA
,
Program Chairs:
Hubertus Franke
IBM Research, USA
,
Paul H.J. Kelly
Imperial College London, UK

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 17 May 2010

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May 17 - 19, 2010

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Cited By

Rahmani ALiljeberg PPlosila JTenhunen H(2013)Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channelsJournal of Computer and System Sciences10.1016/j.jcss.2012.09.00479:4(440-456)Online publication date: 1-Jun-2013
https://dl.acm.org/doi/10.1016/j.jcss.2012.09.004
Rahmani AVaddina KLiljeberg PPlosila JTenhunen H(2011)Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical ChannelsIntegrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation10.1007/978-3-642-24154-3_28(278-287)Online publication date: 2011
https://doi.org/10.1007/978-3-642-24154-3_28
Rahmani ALiljeberg PPlosila JTenhunen H(2010)An efficient VFI-based NoC architecture using Johnson-encoded Reconfigurable FIFOsNORCHIP 201010.1109/NORCHIP.2010.5669474(1-5)Online publication date: Nov-2010
https://doi.org/10.1109/NORCHIP.2010.5669474

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