ABSTRACT
Distributing a single global clock across a chip while meeting the power requirements of the design is a troublesome task due to shrinking technology nodes associated with high clock frequencies. To deal with this, network-on-chip (NoC) architectures partitioned into several voltage-frequency islands (VFIs) have been proposed. To interface the islands on a chip, operating at different frequencies, a complex bi-synchronous FIFO design is inevitable. However, these FIFOs are not needed if adjacent switches belong to the same clock domain. In this paper, a Reconfigurable Synchronous/Bi-Synchronous (RSBS) FIFO is proposed which can adapt its operation to either synchronous or bi-synchronous mode. The FIFO is presented by three different scalable and synthesizable design styles and, in addition, some techniques are suggested to show how the FIFO could be utilized in a VFI-based NoC. Our analysis reveal that the RSBS FIFOs can help to achieve up to 15% savings in the average power consumption of NoC switches and 29% improvement in the total average packet latency in the case of MPEG-4 encoder application, when compared to a non-reconfigurable architecture.
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Index Terms
Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs
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