research-article

ParaLearn: a massively parallel, scalable system for learning interaction networks on FPGAs

Authors:

Narges Bani Asadi,

Christopher W. Fletcher,

John Wawrzynek,

Garry P. NolanAuthors Info & Claims

ICS '10: Proceedings of the 24th ACM International Conference on Supercomputing

Pages 83 - 94

https://doi.org/10.1145/1810085.1810100

Published: 02 June 2010 Publication History

Abstract

ParaLearn is a scalable, parallel FPGA-based system for learning interaction networks using Bayesian statistics. ParaLearn includes problem specific parallel/scalable algorithms, system software and hardware architecture to address this complex problem.

Learning interaction networks from data uncovers causal relationships and allows scientists to predict and explain a system's behavior. Interaction networks have applications in many fields, though we will discuss them particularly in the field of personalized medicine where state of the art high-throughput experiments generate extensive data on gene expression, DNA sequencing and protein abundance. In this paper we demonstrate how ParaLearn models Signaling Networks in human T-Cells.

We show greater than 2000 fold speedup on a Field Programmable Gate Array when compared to a baseline conventional implementation on a General Purpose Processor (GPP), a 2.38 fold speedup compared to a heavily optimized parallel GPP implementation, and between 2.74 and 6.15 fold power savings over the optimized GPP. Through using current generation FPGA technology and caching optimizations, we further project speedups of up to 8.15 fold, relative to the optimized GPP. Compared to software approaches, ParaLearn is faster, more power efficient, and can support novel learning algorithms that substantially improve the precision and robustness of the results.

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Cited By

Banerjee SKalbarczyk ZIyer RBahar IHerlihy MWitchel ELebeck A(2019)AcMC 2 Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3297858.3304019(515-528)Online publication date: 4-Apr-2019
https://dl.acm.org/doi/10.1145/3297858.3304019
Darvish Rouhani BGhasemzadeh MKoushanfar FAnderson JBazargan K(2018)CausaLearnProceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3174243.3174259(1-10)Online publication date: 15-Feb-2018
https://dl.acm.org/doi/10.1145/3174243.3174259
Lebedev IFletcher CCheng SMartin JDoupnik ABurke DLin MWawrzynek J(2012)Exploring many-core design templates for FPGAs and ASICsInternational Journal of Reconfigurable Computing10.1155/2012/4391412012(8-8)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1155/2012/439141
Show More Cited By

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Published In

cover image ACM Conferences

ICS '10: Proceedings of the 24th ACM International Conference on Supercomputing

June 2010

365 pages

ISBN:9781450300186

DOI:10.1145/1810085

General Chair:
Taisuke Boku
University of Tsukuba
,
Program Chairs:
Hiroshi Nakashima
Kyoto University
,
Avi Mendelson
Microsoft

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGARCH: ACM Special Interest Group on Computer Architecture

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Association for Computing Machinery

New York, NY, United States

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Published: 02 June 2010

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National Institutes of Health

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ICS'10

Sponsor:

SIGARCH

ICS'10: International Conference on Supercomputing

June 2 - 4, 2010

Ibaraki, Tsukuba, Japan

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Overall Acceptance Rate 629 of 2,180 submissions, 29%

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Cited By

Banerjee SKalbarczyk ZIyer RBahar IHerlihy MWitchel ELebeck A(2019)AcMC 2 Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3297858.3304019(515-528)Online publication date: 4-Apr-2019
https://dl.acm.org/doi/10.1145/3297858.3304019
Darvish Rouhani BGhasemzadeh MKoushanfar FAnderson JBazargan K(2018)CausaLearnProceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3174243.3174259(1-10)Online publication date: 15-Feb-2018
https://dl.acm.org/doi/10.1145/3174243.3174259
Lebedev IFletcher CCheng SMartin JDoupnik ABurke DLin MWawrzynek J(2012)Exploring many-core design templates for FPGAs and ASICsInternational Journal of Reconfigurable Computing10.1155/2012/4391412012(8-8)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1155/2012/439141
Fletcher CLebedev IAsadi NBurke DWawrzynek JWawrzynek JCompton K(2011)Bridging the GPGPU-FPGA efficiency gapProceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1950413.1950439(119-122)Online publication date: 27-Feb-2011
https://dl.acm.org/doi/10.1145/1950413.1950439
Linderman MBruggner RAthalye VMeng TBani Asadi NNolan GBoku TNakashima HMendelson A(2010)High-throughput Bayesian network learning using heterogeneous multicore computersProceedings of the 24th ACM International Conference on Supercomputing10.1145/1810085.1810101(95-104)Online publication date: 2-Jun-2010
https://dl.acm.org/doi/10.1145/1810085.1810101
Lebedev ICheng SDoupnik AMartin JFletcher CBurke DLin MWawrzynek J(2010)MARCProceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs10.1109/ReConFig.2010.49(7-12)Online publication date: 13-Dec-2010
https://dl.acm.org/doi/10.1109/ReConFig.2010.49

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