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Coordinated power management of voltage islands in CMPs

Published: 14 June 2010 Publication History

Abstract

Multiple clock domain architectures have recently been proposed to alleviate the power problem in CMPs by having different frequency/voltage values assigned to each domain based on workload requirements. However, accurate allocation of power to these voltage/frequency islands based on time varying workload characteristics as well as controlling the power consumption at the provisioned power level is non-trivial. Toward this end, we propose a two-tier feedback-based control theoretic solution. Our first-tier consists of a global power manager that allocates power targets to individual islands based on the workload dynamics. The power consumptions of these islands are in turn controlled by a second-tier, consisting of local controllers that regulate island power using dynamic voltage and frequency scaling in response to workload requirements.

Reference

[1]
K. Skadron, M. R. Stan, K. Sankaranarayanan, W. H. S. Velusamy and D. Tarjan. Temperature-aware Microarchitecture: Modeling and Implementation. ACM Trans. Archit. Code Optim. (TACO), 2004

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  • (2011)Scalable power control for many-core architectures running multi-threaded applicationsACM SIGARCH Computer Architecture News10.1145/2024723.200011739:3(449-460)Online publication date: 4-Jun-2011
  • (2011)Scalable power control for many-core architectures running multi-threaded applicationsProceedings of the 38th annual international symposium on Computer architecture10.1145/2000064.2000117(449-460)Online publication date: 4-Jun-2011
  • (2018)Energy Efficient Real Time Scheduling on Multi-core Processor with Voltage Islands2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI)10.1109/ICACCI.2018.8554680(1245-1251)Online publication date: Sep-2018
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    Published In

    cover image ACM Conferences
    SIGMETRICS '10: Proceedings of the ACM SIGMETRICS international conference on Measurement and modeling of computer systems
    June 2010
    398 pages
    ISBN:9781450300384
    DOI:10.1145/1811039
    • cover image ACM SIGMETRICS Performance Evaluation Review
      ACM SIGMETRICS Performance Evaluation Review  Volume 38, Issue 1
      Performance evaluation review
      June 2010
      382 pages
      ISSN:0163-5999
      DOI:10.1145/1811099
      Issue’s Table of Contents

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 14 June 2010

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    Author Tags

    1. DVFs
    2. GALs
    3. chip multiprocessors (CMP)
    4. control theory

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    Overall Acceptance Rate 459 of 2,691 submissions, 17%

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    View all
    • (2011)Scalable power control for many-core architectures running multi-threaded applicationsACM SIGARCH Computer Architecture News10.1145/2024723.200011739:3(449-460)Online publication date: 4-Jun-2011
    • (2011)Scalable power control for many-core architectures running multi-threaded applicationsProceedings of the 38th annual international symposium on Computer architecture10.1145/2000064.2000117(449-460)Online publication date: 4-Jun-2011
    • (2018)Energy Efficient Real Time Scheduling on Multi-core Processor with Voltage Islands2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI)10.1109/ICACCI.2018.8554680(1245-1251)Online publication date: Sep-2018
    • (2015)Investigation of DVFS based dynamic reliability management for chip multiprocessors2015 International Conference on High Performance Computing & Simulation (HPCS)10.1109/HPCSim.2015.7237093(563-568)Online publication date: Jul-2015

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