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Characterizing the soft error vulnerability of multicores running multithreaded applications

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SIGMETRICS '10: Proceedings of the ACM SIGMETRICS international conference on Measurement and modeling of computer systems

Pages 379 - 380

https://doi.org/10.1145/1811039.1811096

Published: 14 June 2010 Publication History

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Abstract

Multicores have become the platform of choice across all market segments. Cost-effective protection against soft errors is important in these environments, due to the need to move to lower technology generations and the exploding number of transistors on a chip. While multicores offer the flexibility of varying the number of application threads and the number of cores on which they run, the reliability impact of choosing one configuration over another is unclear. Our study reveals that the reliability costs vary dramatically between configurations and being unaware could lead to a sub-optimal choice.

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Cited By

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Oz ITopcuoglu HKandemir MTosun O(2018)Reliability-aware core partitioning in chip multiprocessorsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2012.02.00558:3-4(160-176)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1016/j.sysarc.2012.02.005
Pouyan FAzarpeyvand ASafari SFakhraie S(2018)Reliability aware throughput management of chip multi-processor architecture via thread migrationThe Journal of Supercomputing10.1007/s11227-016-1665-372:4(1363-1380)Online publication date: 31-Dec-2018
https://dl.acm.org/doi/10.1007/s11227-016-1665-3
Duan LZhang YLi BPeng L(2014)Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal RulesIEEE Transactions on Computers10.1109/TC.2013.2463:9(2201-2214)Online publication date: Sep-2014
https://doi.org/10.1109/TC.2013.24
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Index Terms

Characterizing the soft error vulnerability of multicores running multithreaded applications
1. Hardware
  1. Hardware test
  2. Robustness

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Characterizing the soft error vulnerability of multicores running multithreaded applications
Performance evaluation review

Multicores have become the platform of choice across all market segments. Cost-effective protection against soft errors is important in these environments, due to the need to move to lower technology generations and the exploding number of transistors ...
Utility-based acceleration of multithreaded applications on asymmetric CMPs
ICSA '13

Asymmetric Chip Multiprocessors (ACMPs) are becoming a reality. ACMPs can speed up parallel applications if they can identify and accelerate code segments that are critical for performance. Proposals already exist for using coarse-grained thread ...
Utility-based acceleration of multithreaded applications on asymmetric CMPs
ISCA '13: Proceedings of the 40th Annual International Symposium on Computer Architecture

Asymmetric Chip Multiprocessors (ACMPs) are becoming a reality. ACMPs can speed up parallel applications if they can identify and accelerate code segments that are critical for performance. Proposals already exist for using coarse-grained thread ...

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Published In

SIGMETRICS '10: Proceedings of the ACM SIGMETRICS international conference on Measurement and modeling of computer systems

June 2010

398 pages

ISBN:9781450300384

DOI:10.1145/1811039

General Chair:
Vishal Misra
Columbia University, USA
,
Program Chairs:
Paul Barford
University of Wisconsin-Madison, USA
,
Mark Squillante
IBM T.J. Watson Research Center, USA

ACM SIGMETRICS Performance Evaluation Review Volume 38, Issue 1
Performance evaluation review
June 2010
382 pages
ISSN:0163-5999
DOI:10.1145/1811099
Issue’s Table of Contents

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 14 June 2010

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SIGMETRICS '10

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SIGMETRICS

SIGMETRICS '10: ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems

June 14 - 18, 2010

New York, New York, USA

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Overall Acceptance Rate 459 of 2,691 submissions, 17%

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Cited By

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Oz ITopcuoglu HKandemir MTosun O(2018)Reliability-aware core partitioning in chip multiprocessorsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2012.02.00558:3-4(160-176)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1016/j.sysarc.2012.02.005
Pouyan FAzarpeyvand ASafari SFakhraie S(2018)Reliability aware throughput management of chip multi-processor architecture via thread migrationThe Journal of Supercomputing10.1007/s11227-016-1665-372:4(1363-1380)Online publication date: 31-Dec-2018
https://dl.acm.org/doi/10.1007/s11227-016-1665-3
Duan LZhang YLi BPeng L(2014)Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal RulesIEEE Transactions on Computers10.1109/TC.2013.2463:9(2201-2214)Online publication date: Sep-2014
https://doi.org/10.1109/TC.2013.24
Oz ITopcuoglu HKandemir MTosun O(2013)Examining Thread Vulnerability analysis using fault-injection2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2013.6673282(240-245)Online publication date: Oct-2013
https://doi.org/10.1109/VLSI-SoC.2013.6673282
Duan LPeng LLi B(2013)Predicting Architectural Vulnerability on Multithreaded Processors under Resource Contention and SharingIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2012.8710:2(114-127)Online publication date: 1-Mar-2013
https://dl.acm.org/doi/10.1109/TDSC.2012.87
Yan JZhang W(2011)Computing and Reducing Transient Error Propagation in RegistersJournal of Computing Science and Engineering10.5626/JCSE.2011.5.2.1215:2(121-130)Online publication date: 30-Jun-2011
https://doi.org/10.5626/JCSE.2011.5.2.121
Duan LZhang YLi BPeng L(2011)Universal rules guided design parameter selection for soft error resilient processors(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE10.1109/ISPASS.2011.5762741(247-256)Online publication date: Apr-2011
https://doi.org/10.1109/ISPASS.2011.5762741
Oz ITopcuoglu HKandemir MTosun O(2019)Thread vulnerability in parallel applicationsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2012.05.00272:10(1171-1185)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.1016/j.jpdc.2012.05.002
Duan LZhang YLi BPeng L(2014)Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal RulesIEEE Transactions on Computers10.1109/TC.2013.2463:9(2201-2214)Online publication date: Sep-2014
https://doi.org/10.1109/TC.2013.24

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