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Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs

Authors:

Dae Hyun Kim,

Sung Kyu LimAuthors Info & Claims

SLIP '10: Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction

Pages 25 - 32

https://doi.org/10.1145/1811100.1811108

Published: 13 June 2010 Publication History

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Abstract

In this paper, we present a delay and power prediction model for buffered interconnects used in 3D ICs. The key idea is to model the impact of RC parasitics of Through-Silicon Vias (TSVs) used in 3D interconnects on delay and power consumption. Due to its large size compared with other layout objects such as metal wires, TSVs contain significant RC parasitics, which directly affect the overall delay and power of the wires that contain them. On the other hand, buffer insertion on TSV-based 3D interconnects is also non-trivial mainly because buffers as well as TSVs have non-trivial area overhead. In addition, both TSVs and buffers occupy device and M1 layers, thereby becoming layout obstacles to each other. Our interconnect model accurately captures the impact of both TSVs and buffers on 3D interconnects.

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Cited By

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Cheng XZhou JZhang ZYu W(2024)An Analytical GPU-Enabled Framework for the Stacked 3D IC LayoutsJournal of Circuits, Systems and Computers10.1142/S021812662450281533:16Online publication date: 10-Jun-2024
https://doi.org/10.1142/S0218126624502815
Bamberg LJoseph JGarcía-Ortiz APionteck TBamberg LJoseph JGarcía-Ortiz APionteck T(2022)Low-Power Technique for 3D Interconnects3D Interconnect Architectures for Heterogeneous Technologies10.1007/978-3-030-98229-4_8(155-176)Online publication date: 12-Mar-2022
https://doi.org/10.1007/978-3-030-98229-4_8
Bamberg LJoseph JGarcía-Ortiz APionteck TBamberg LJoseph JGarcía-Ortiz APionteck T(2022)High-Level Formulas for the 3D-Interconnect Power Consumption and Performance3D Interconnect Architectures for Heterogeneous Technologies10.1007/978-3-030-98229-4_3(51-70)Online publication date: 12-Mar-2022
https://doi.org/10.1007/978-3-030-98229-4_3
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Index Terms

Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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Published In

SLIP '10: Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction

June 2010

106 pages

ISBN:9781450300377

DOI:10.1145/1811100

General Chair:
Sherief Reda
Brown University, USA
,
Program Chair:
Janet Wang
University of Arizona, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 13 June 2010

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SLIP '10: System Level Interconnect Prediction Workshop

June 13, 2010

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Cheng XZhou JZhang ZYu W(2024)An Analytical GPU-Enabled Framework for the Stacked 3D IC LayoutsJournal of Circuits, Systems and Computers10.1142/S021812662450281533:16Online publication date: 10-Jun-2024
https://doi.org/10.1142/S0218126624502815
Bamberg LJoseph JGarcía-Ortiz APionteck TBamberg LJoseph JGarcía-Ortiz APionteck T(2022)Low-Power Technique for 3D Interconnects3D Interconnect Architectures for Heterogeneous Technologies10.1007/978-3-030-98229-4_8(155-176)Online publication date: 12-Mar-2022
https://doi.org/10.1007/978-3-030-98229-4_8
Bamberg LJoseph JGarcía-Ortiz APionteck TBamberg LJoseph JGarcía-Ortiz APionteck T(2022)High-Level Formulas for the 3D-Interconnect Power Consumption and Performance3D Interconnect Architectures for Heterogeneous Technologies10.1007/978-3-030-98229-4_3(51-70)Online publication date: 12-Mar-2022
https://doi.org/10.1007/978-3-030-98229-4_3
Mohapatra SVendra SChrzanowska-Jeske M(2021)Fast Buffer Count Estimation in 3D IC FloorplanningIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2020.300785868:1(271-275)Online publication date: Jan-2021
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Takawadekar VVaidya Y(2021)Neuromorphic computing: Modelling of 3D integrated circuit components using TSV2021 12th International Conference on Computing Communication and Networking Technologies (ICCCNT)10.1109/ICCCNT51525.2021.9579593(1-7)Online publication date: 6-Jul-2021
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Mohapatra SVendra SChrzanowska-Jeske M(2018)Through Silicon Via-Aware Layout Design and Power Estimation in Sub-45 Nanometer 3D CMOS IC Technologies2018 IEEE 13th Nanotechnology Materials and Devices Conference (NMDC)10.1109/NMDC.2018.8605914(1-4)Online publication date: Oct-2018
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Voicu GCotofana S(2017)High-Performance, Cost-Effective 3D Stacked Wide-Operand AddersIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2016.25982905:2(179-192)Online publication date: 1-Apr-2017
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Kalargaris HChen YPavlidis V(2017)STA compatible backend design flow for TSV-based 3-D ICs2017 18th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2017.7918314(186-190)Online publication date: Mar-2017
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Grani PProietti RAkella VBen Yoo SJacob B(2016)Photonic Interconnects for Interposer-based 2.5D/3D Integrated Systems on a ChipProceedings of the Second International Symposium on Memory Systems10.1145/2989081.2989111(377-386)Online publication date: 3-Oct-2016
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Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs

Effect of TSV fabrication technology on power distribution in 3D ICs

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