Jinhai Qiu
ABSTRACT
We propose in this paper a novel approach for speeding timing closure. We focus on the problem of accurate post-routing delay estimation from a given placement. Post-routing delays differ from placement delays due to factors such as net topology, layer assignment and congestion. Fundamental to our approach is utilizing an existing base design to predict future designs. We present four wire-delay estimation techniques based on: delay fitting, Steiner-aware delay fitting, Steiner-aware RC sampling, and scaled Steiner-aware RC sampling. We apply our techniques to several designs, and using an industrial flow, we demonstrate that it is possible to estimate the routing delays with an average estimation error of 16% on benchmark circuits. These results are of practical value, and improve on the state-of-the-art industrial estimation capabilities.
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Index Terms
- Fast, accurate a priori routing delay estimation
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