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View all- Mittal S(2016)A survey of techniques for architecting TLBsConcurrency and Computation: Practice and Experience10.1002/cpe.406129:10Online publication date: 22-Dec-2016
B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems
Article No.: 2, Pages 1 - 10
Abstract
High performance embedded processors are equipped with the Translation Look-aside Buffer (TLB) which forms the key ingredient to efficient and speedy virtual memory management. The TLB though small, is frequently accessed, and therefore not only consumes significant energy, but also is one of the important thermal hot-spots in the processor. Among the many circuit and microarchitectural techniques proposed to reduce TLB power consumption, the Use-Last TLB is one very efficient technique in which power is consumed only when different pages are accessed in succession, i.e., when there is a page-switch [26]. Though the Use-Last technique is effective in reducing i-TLB power, there is scope to further improve its effectiveness by changing the relative code placement of the program. In this work, we formulate the code placement problem to minimize the page-switches in a program. We prove that this problem is NP-complete and propose an efficient Bounds Based Procedure Placement (B2P2) heuristic to efficiently reduce the program's page-switches. Our procedure placement technique delivers an average of 76% reduction in the instrucion-TLB power with negligible (< 2%) impact on performance, over and above the reduction achieved by the Use-Last TLB architecture alone.
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Index Terms
- B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems
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Published: 28 June 2010
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SCOPES '10: 13th International Workshop on Software and Compilers for Embedded Systems
June 28 - 29, 2010
St. Goar, Germany
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View all- Mittal S(2016)A survey of techniques for architecting TLBsConcurrency and Computation: Practice and Experience10.1002/cpe.406129:10Online publication date: 22-Dec-2016
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