research-article

LReplay: a pending period based deterministic replay scheme

Authors:

Ruiyang WuAuthors Info & Claims

ISCA '10: Proceedings of the 37th annual international symposium on Computer architecture

Pages 187 - 197

https://doi.org/10.1145/1815961.1815985

Published: 19 June 2010 Publication History

Abstract

Debugging parallel program is a well-known difficult problem. A promising method to facilitate debugging parallel program is using hardware support to achieve deterministic replay. A hardware-assisted deterministic replay scheme should have a small log size, as well as low design cost, to be feasible for adopting by industrial processors. To achieve the goals, we propose a novel and succinct hardware-assisted deterministic replay scheme named LReplay. The key innovation of LReplay is that instead of recording the logical time orders between instructions or instruction blocks as previous investigations, LReplay is built upon recording the pending period information [6]. According to the experimental results on Godson-3, the overall log size of LReplay is about 0.55B/K-Inst (byte per k-instruction) for sequential consistency, and 0.85B/K-Inst for Godson-3 consistency. The log size is smaller in an order of magnitude than state-of-art deterministic replay schemes incuring no performance loss. Furthermore, LReplay only consumes about $1.3%$ area of Godson-3, since it requires only trivial modifications to the existing components of Godson-3. The above features of LReplay demonstrate the potential of integrating hardware-assisted deterministic replay into future industrial processors.

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Index Terms

LReplay: a pending period based deterministic replay scheme
1. Software and its engineering
  1. Software creation and management
    1. Software verification and validation
      1. Software defect analysis
        Software testing and debugging
2. Theory of computation
  1. Models of computation
    1. Concurrency
      1. Parallel computing models

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cover image ACM Conferences

ISCA '10: Proceedings of the 37th annual international symposium on Computer architecture

June 2010

520 pages

ISBN:9781450300537

DOI:10.1145/1815961

General Chair:
André Seznec
INRIA Rennes
,
Program Chairs:
Uri Weiser
Technion
,
Ronny Ronen
Intel

ACM SIGARCH Computer Architecture News Volume 38, Issue 3
ISCA '10
June 2010
508 pages
ISSN:0163-5964
DOI:10.1145/1816038
Issue’s Table of Contents

Copyright © 2010 ACM.

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Published: 19 June 2010

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https://dl.acm.org/doi/10.1145/3582016.3582040
Hoshino SArahori YGondow KHung CHong JBechini ASong E(2021)STRABProceedings of the 36th Annual ACM Symposium on Applied Computing10.1145/3412841.3442028(1532-1541)Online publication date: 22-Mar-2021
https://dl.acm.org/doi/10.1145/3412841.3442028
Tian CChen CDuan ZZhao L(2019)Differential Testing of Certificate Validation in SSL/TLS ImplementationsACM Transactions on Software Engineering and Methodology10.1145/335504828:4(1-37)Online publication date: 9-Oct-2019
https://dl.acm.org/doi/10.1145/3355048
Kim YMun SYoo SKim M(2019)Precise Learn-to-Rank Fault Localization Using Dynamic and Static Features of Target ProgramsACM Transactions on Software Engineering and Methodology10.1145/334562828:4(1-34)Online publication date: 9-Oct-2019
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