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Conflict exceptions: simplifying concurrent language semantics with precise hardware exceptions for data-races

Published: 19 June 2010 Publication History

Abstract

We argue in this paper that concurrency errors should be treated as exceptions, i.e., have fail-stop behavior and precise semantics. We propose an exception model based on conflict of synchronization free regions, which precisely detects a broad class of data-races. We show that our exceptions provide enough guarantees to simplify high-level programming language semantics and debugging, but are significantly cheaper to enforce than traditional data-race detection. To make the performance cost of enforcement negligible, we propose architecture support for accurately detecting and precisely delivering these exceptions. We evaluate the suitability of our model as well as the behavior of our architectural mechanisms using the PARSEC benchmark suite and commercial applications. Our results show that the exception model largely reflects how programmers are already writing code and that the main memory, traffic and performance overheads of the enforcement mechanisms we propose are very low.

References

[1]
M. Abadi, C. Flanagan, and S. Freund. Types for Safe Locking: Static Race Detection for Java. ACM Transactions on Programming Languages and Systems (TOPLAS), 2006.
[2]
S. V. Adve and H.-J. Boehm. Memory Models: A Case for Rethinking Parallel Languages and Hardware. to appear, CACM; authors' preliminary version at http://rsim.cs.uiuc.edu/Pubs/10-cacm-memory-models.pdf.
[3]
S. V. Adve and K. Gharachorloo. Shared Memory Consistency Models: A Tutorial. IEEE Computer, 29(12), 1996.
[4]
S. V. Adve and M. D. Hill. Weak Ordering---A New Definition. In International Symposium on Computer Architecture (ISCA), 1990.
[5]
S. V. Adve, M. D. Hill, B. P. Miller, and R. H. B. Netzer. Detecting Data Races on Weak Memory Systems. In International Symposium on Computer Architecture (ISCA), 1991.
[6]
C. S. Ananian, Krste Asanovic, B. C. Kuszmaul, C. E. Leiserson, and S. Lie. Unbounded Transactional Memory. In International Symposium on High-Performance Computer Architecture (HPCA), February 2005.
[7]
T. Andrews, S. Qadeer, S. K. Rajamani, J. Rehof, and Y. Xie. Zing: Exploiting Program Structure for Model Checking Concurrent Software. In CONCUR, 2003.
[8]
D. Aspinall and J. Sevcik. Java Memory Model Examples: Good, Bad, and Ugly. In VAMP, 2007.
[9]
C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC Benchmark Suite: Characterization and Architectural Implications. In International Conference on Parallel Architectures and Compilation Techniques (PACT), 2008.
[10]
J. Bobba, N. Goyal M. D. Hill, M. M. Swift, and D. A. Wood. TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory. In International Symposium on Computer Architecture (ISCA), 2008.
[11]
R. Bocchino, V. Adve, D. Dig, S. Adve, S. Heumann, R. Komuravelli, J. Overbey, P. Simmons, H. Sung, and M. Vakilian. A type and effect system for deterministic parallel Java. In Conference on Object-Oriented Programming Systems, Languages and Applications (OOPSLA), October 2009.
[12]
H. Boehm. Simple Thread Semantics Require Race Detection. PLDI FIT, 2009.
[13]
H.-J. Boehm and S. V. Adve. Foundations of the C++ Concurrency Memory Model. In Conference on Programming Language Design and Implementation (PLDI), 2008.
[14]
L. Ceze, J. Devietti, B. Lucia, and S. Qadeer. A Case for System Support for Concurrency Exceptions. In USENIX HotPar, 2009.
[15]
L. Ceze, J. Tuck, P. Montesinos, and J. Torrellas. BulkSC: Bulk Enforcement of Sequential Consistency. In International Symposium on Computer Architecture (ISCA), 2007.
[16]
T. Elmas, S. Qadeer, and S. Tasiran. Goldilocks: a Race and Transaction-aware Java Runtime. In Conference on Programming Language Design and Implementation (PLDI), 2007.
[17]
C. Flanagan and S. Freund. FastTrack: Efficient and Precise Dynamic Race Detection. In Conference on Programming Language Design and Implementation (PLDI), 2009.
[18]
C. Gniady, B. Falsafi, and T. N. Vijaykumar. Is SC + ILP = RC? In International Symposium on Computer Architecture (ISCA), May 1999.
[19]
P. B. Hansen. The programming language Concurrent Pascal. IEEE Transactions on Software Engineering, June 1975.
[20]
IBM, Intel, and Sun. Draft specification of transactional language constructs for C++, version 1.0. http://software.intel.com/file/21569, August 2009.
[21]
IEEE and The Open Group. IEEE Standard 1003.1-2001, 2001.
[22]
ISO/IEC JTC1/SC22/WG21. ISO/IEC 14882, Programming Language - C++ (Final Committee Draft). http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2010/n3092.pdf, March 2010.
[23]
L. Lamport. How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs. IEEE Transactions on Computers, 1979.
[24]
J. Lee and D. Padua. Hiding Relaxed Memory Consistency with Compilers. In International Conference on Parallel Architectures and Compilation Techniques (PACT), 2000.
[25]
S. Lu, J. Tucek, F. Qin, and Y. Zhou. AVIO: Detecting Atomicity Violations via Access Interleaving Invariants. In International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2006.
[26]
C. K. Luk, R. S. Cohn, R. Muth, H. Patil, A. Klauser, P. G. Lowney, S. Wallace, V. J. Reddi, and K. M. Hazelwood. PIN: Building Customized Program Analysis Tools with Dynamic Instrumentation. In Conference on Programming Language Design and Implementation (PLDI), 2005.
[27]
J. Manson, W. Pugh, and S. Adve. The Java Memory Model. In Symposium on Principles of Programming Languages (POPL), 2005.
[28]
D. Marino, A. Singh, T. Millstein, M. Musuvathi, and S. Narayanasamy. DRFx: A Simple and Efficient Memory Model for Concurrent Programming Languages. In Conference on Programming Language Design and Implementation (PLDI), 2010.
[29]
J. F. Martínez, J. Renau, M.C. Huang, M. Prvulovic, and J. Torrellas. Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors. In International Symposium on Microarchitecture (MICRO), November 2002.
[30]
K. Moore, K. E. Moore, J. Bobba, M. J. Moravan, M. D. Hill, and D. A. Wood. LogTM: Log-based Transactional Memory. In International Symposium on High-Performance Computer Architecture (HPCA), 2006.
[31]
A. Muzahid, D. Suarez, S. Qi, and J. Torrellas. SigRace: Signature-Based Data Race Detection. In International Symposium on Computer Architecture (ISCA), 2009.
[32]
C. Nelson and H.-J. Boehm. Concurrency Memory Model (final revision). C++ standards committee paper WG21/N2429=J16/07-0299, http://www.open-std.org/JTC1/SC22/WG21/docs/papers/2007/n2429.htm, October 2007.
[33]
M. Prvulovic and J. Torrellas. ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes. In International Symposium on Computer Architecture (ISCA), 2003.
[34]
W. Pugh. The Java Memory Model is Fatally Flawed. Concurrency - Practice and Experience, 12(6), 2000.
[35]
R. Rajwar, M. Herlihy, and K. Lai. Virtualizing Transactional Memory. In International Symposium on Computer Architecture (ISCA), 2005.
[36]
J. Renau, B. Fraguela, J. Tuck, W. Liu, M. Prvulovic, L. Ceze, S. Sarangi, P. Sack, K. Strauss, and P. Montesinos. SESC Simulator, January 2005. http://sesc.sourceforge.net.
[37]
J. Sevcik and D. Aspinall. On Validity of Program Transformations in the Java Memory Model. In European Conference on Object-Oriented Programming (ECOOP), 2008.
[38]
D. Shasha and M. Snir. Efficient and correct execution of parallel programs that share memory. ACM Transactions on Programming Languages and Systems (TOPLAS), April 1988.
[39]
United States Department of Defense. Reference Manual for the Ada Programming Language: ANSI/MIL-STD-1815A-1983 Standard 1003.1-2001, 1983. Springer.
[40]
E. Vallejo, M. Galluzzi, A. Cristal, F. Vallejo, R. Beivide, P. Stenstrom, J. E. Smith, and M. Valero. Implementing Kilo-Instruction Multiprocessors. In International Conference on Pervasive Services (ICPS), 2005.
[41]
T. F. Wenisch, A. Ailamaki, B. Falsafi, and A. Moshovos. Mechanisms for Store-wait-free Multiprocessors. In International Symposium on Computer Architecture (ISCA), 2007.
[42]
P. Zhou, R. Teodorescu, and Y. Zhou. HARD: Hardware-Assisted Lockset-based Race Detection. In International Symposium on High-Performance Computer Architecture (HPCA), 2007. International Symposium on High-Performance Computer Architecture (HPCA), 2007.

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Published In

cover image ACM Conferences
ISCA '10: Proceedings of the 37th annual international symposium on Computer architecture
June 2010
520 pages
ISBN:9781450300537
DOI:10.1145/1815961
  • cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 38, Issue 3
    ISCA '10
    June 2010
    508 pages
    ISSN:0163-5964
    DOI:10.1145/1816038
    Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 19 June 2010

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Author Tags

  1. bug detection
  2. data-races
  3. memory consistency models
  4. multicores
  5. threads

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  • (2022)Yashme: detecting persistency racesProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507766(830-845)Online publication date: 28-Feb-2022
  • (2021)Kard: lightweight data race detection with per-thread memory protectionProceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3445814.3446727(647-660)Online publication date: 19-Apr-2021
  • (2021)C11Tester: a race detector for C/C++ atomicsProceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3445814.3446711(630-646)Online publication date: 19-Apr-2021
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