Xiaodong Liu
ABSTRACT
This paper describes a solution for global routing and track assignment of flip-chip I/O nets. Voronoi Diagram (VD) is used to partition the open routing space and the geometrical properties of VD graph are exploited to create global routing channels with capacity and congestion considerations. A network flow algorithm is used to achieve optimal global routing. The regularity of the flip-chip bump placement is observed and allows us to reduce the size of global routing channel graph by over 50% to speed up computation. A track assignment algorithm avoids crossing wires before completing the final route with a detailed router. Experiment results using actual silicon chip data demonstrate that our solution achieves good quality of results compared to an implementation used in a commercial tool.
- J. W. Fang, I. J. Lin, Y. W. Chang, and J. H. Wang. A network-flow-based rdl routing algorithmz for flip-chip design. IEEE Trans. on CAD of Integrated Circuits and Systems, 26(8):1417--1429, 2007. Google Scholar
Digital Library
- J. W. Fang, C. H. Hsu, and Y. W. Chang. An integer-linear-programming-based routing algorithm for flip-chip designs. IEEE Trans. on CAD of Integrated Circuits and Systems, 28(1):98--110, 2009. Google ScholarDigital Library
- J. W. Fang, D. F. Wong, and Y. W. Chang. Flip-chip routing with unified area-i/o pad assignments for package-board co-design. In Proceedings of ACM/IEEE Design Automation Conference, pages 336--339, 2009. Google ScholarDigital Library
- S. J. Fortune. A sweepline algorithm for voronoi diagrams. Algorithmica, 2:153--174, 1987.Google ScholarDigital Library
- R. K. Ahuja, T. L. Magnanti, and J. B. Orlin. Network Flows: Theory, Algorithms and Applications. Prentice-Hall, 1993. Google ScholarDigital Library
- Mark de Berg, Marc van Kreveld, Mark Overmars, and Otfried Schwarzkopf. Computational Geometry. Springer-Verlag, 2nd edition, 2000.Google Scholar
Index Terms
- Global routing and track assignment for flip-chip designs
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