skip to main content
10.1145/1837274.1837315acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
research-article

Virtual channels vs. multiple physical networks: a comparative analysis

Published: 13 June 2010 Publication History

Abstract

Packet-switched networks-on-chip (NoC) have been proposed as an efficient communication infrastructure for multi-core architectures. Adding virtual channels to a NoC helps to avoid deadlock and optimize the bandwidth of the physical channels in exchange for a more complex design of the routers. Another, possibly alternative, approach is to build multiple parallel physical networks (multiplanes) with smaller channels and simpler router organizations. We present a comparative analysis of these two approaches based on analytical models and on a comprehensive set of experimental results including both synthesized hardware implementations and system-level simulations.

References

[1]
J. Owens et al., "Research challenges for on-chip interconnection networks," IEEE Micro, vol. 27, no. 5, pp. 96--108, Sept.-Oct. 2007.
[2]
W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2004.
[3]
L.-S. Peh and W. J. Dally, "A delay model for router microarchitectures," IEEE Micro, vol. 21, pp. 26--34, Jan. 2001.
[4]
L.-S. Peh et al., "In-network snoop ordering (INSO): Snoopy coherence on unordered interconnects," in Int. Sym. on High Perf. Computer Architecture (HPCA), Feb. 2009, pp. 67--78.
[5]
M. B. Taylor et al., "The Raw microprocessor: A computational fabric for software circuits and general purpose programs," IEEE Micro, vol. 22, no. 2, Mar-Apr 2002.
[6]
J. Balfour and W. J. Dally, "Design tradeoffs for tiled CMP on-chip networks," in Conf. on Supercomputing, Nov. 2006, pp. 187--198.
[7]
E. Carara et al., "Router architecture for high-performance NoCs," in Proc. of the Conf. on Integrated circuits and systems design, Jan. 2007, pp. 111--116.
[8]
S. Noh et al., "Multiplane virtual channel router for network-on-chip design," in Int. Conf. on Communications and Electronics, Oct. 2006, pp. 348--351.
[9]
N. Concer et al., "Distributed flit-buffer flow control for networks-on-chip," in Proc. of the Int. Conf. on HW/SW Codesign & System Synthesis, Sep. 2008, pp. 215--220.
[10]
Website, www.opencores.org/.
[11]
P. S. Magnusson et al., "Simics: A full system simulation platform," IEEE Computer, vol. 35, no. 2, pp. 50--58, Feb. 2002.
[12]
M. M. K. Martin et al., "Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset," SIGARCH Comput. Architecture News, vol. 33, no. 4, pp. 92--99, Nov. 2005.
[13]
L.-S. Peh et al., "GARNET: A detailed on-chip network model inside a full-system simulator," in Int. Symp. on Perf. Analysis of Systems and Software, Apr. 2009, pp. 33--42.
[14]
C. Bienia et al., "The PARSEC benchmark suite: characterization and architectural implications," in Conf. on Parallel arch. and compilation techniques, Oct. 2008, pp. 72--81.
[15]
S. Thoziyoor et al., "CACTI 5.1," HP, Tech. Rep., 2008.
[16]
B. Jackob, S. W. Ng, and D. Wang, Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann, 2007.
[17]
Y. H. Song and T. M. Pinkston, "A progressive approach to handling message-dependent deadlock in parallel computer systems," IEEE Trans. on Par. and Dist. Systems, vol. 14, no. 3, pp. 259--275, Mar. 2003.

Cited By

View all
  • (2023)Hybrid, Asymmetric and Reconfigurable Input Unit Designs for Energy-Efficient On-Chip NetworksIEICE Transactions on Electronics10.1587/transele.2022CTP0005E106.C:10(570-579)Online publication date: 1-Oct-2023
  • (2023)SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCsIEEE Design & Test10.1109/MDAT.2023.331035540:6(64-75)Online publication date: Dec-2023
  • (2023)Adaptive distribution of control messages for improving bandwidth utilization in multiple NoCThe Journal of Supercomputing10.1007/s11227-023-05208-079:15(17208-17246)Online publication date: 7-May-2023
  • Show More Cited By

Index Terms

  1. Virtual channels vs. multiple physical networks: a comparative analysis

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    DAC '10: Proceedings of the 47th Design Automation Conference
    June 2010
    1036 pages
    ISBN:9781450300025
    DOI:10.1145/1837274
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 13 June 2010

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. channel slicing
    2. network-on-chip
    3. virtual channel

    Qualifiers

    • Research-article

    Conference

    DAC '10
    Sponsor:

    Acceptance Rates

    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

    Upcoming Conference

    DAC '25
    62nd ACM/IEEE Design Automation Conference
    June 22 - 26, 2025
    San Francisco , CA , USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)13
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 10 Feb 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2023)Hybrid, Asymmetric and Reconfigurable Input Unit Designs for Energy-Efficient On-Chip NetworksIEICE Transactions on Electronics10.1587/transele.2022CTP0005E106.C:10(570-579)Online publication date: 1-Oct-2023
    • (2023)SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCsIEEE Design & Test10.1109/MDAT.2023.331035540:6(64-75)Online publication date: Dec-2023
    • (2023)Adaptive distribution of control messages for improving bandwidth utilization in multiple NoCThe Journal of Supercomputing10.1007/s11227-023-05208-079:15(17208-17246)Online publication date: 7-May-2023
    • (2022)FlitZip: Effective Packet Compression for NoC in MultiProcessor System-on-ChipIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.309031533:1(117-128)Online publication date: 1-Jan-2022
    • (2022)A router architecture with dual input and dual output channels for Networks-on-ChipMicroprocessors & Microsystems10.1016/j.micpro.2022.10446490:COnline publication date: 1-Apr-2022
    • (2021)A survey on emerging issues in interconnection networksInternational Journal of Internet Technology and Secured Transactions10.1504/ijitst.2021.11351211:2(131-159)Online publication date: 1-Jan-2021
    • (2021)Topology Agnostic Virtual Channel Assignment and Protocol Level Deadlock Avoidance in a Network-on-Chip2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586196(61-66)Online publication date: 5-Dec-2021
    • (2020)Automated synthesis of custom networks-on-chip for real world applicationsProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415656(1-9)Online publication date: 2-Nov-2020
    • (2020)Characterization of Subnets, Virtual Channel and Routing on Wireless Network-on-Chip Performance2020 IEEE Student Conference on Research and Development (SCOReD)10.1109/SCOReD50371.2020.9250968(117-121)Online publication date: 27-Sep-2020
    • (2020)Off-Chip Congestion Management for GPU-based Non-Uniform Processing-in-Memory Networks2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)10.1109/PDP50117.2020.00050(282-289)Online publication date: Mar-2020
    • Show More Cited By

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media