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Theoretical analysis of gate level information flow tracking

Published: 13 June 2010 Publication History

Abstract

Understanding the flow of information is an important aspect in computer security. There has been a recent move towards tracking information in hardware and understanding the flow of individual bits through Boolean functions. Such gate level information flow tracking (GLIFT) provides a precise understanding of all flows of information. This paper presents a theoretical analysis of GLIFT. It formalizes the problem, provides fundamental definitions and properties, introduces precise symbolic representations of the GLIFT logic for basic Boolean functions, and gives analytic and quantitative analysis of the GLIFT logic.

References

[1]
D. Volpano, C. Irvine, and G. Smith "A sound type system for secure flow analysis," in Journal of Computer Security, 4(2--3):167--187, 1996.
[2]
A. Sabelfeld and A. C. Myers. "Language-based information-flow security," IEEE Journal on Selected Areas in Communications, 21:2003, 2003.
[3]
A. C. Myers, N. Nystrom, L. Zheng, and S. Zdancewic. Jif: Java information flow. Software release. http://www.cs.cornell.edu/jif, July 2001.
[4]
G. E. Suh, J. W. Lee, D. Zhang, and S. Devadas. "Secure Program Execution via Dynamic Information Flow Tracking," In ASPLOS-XI: Proceedings of the 11th international conference on Architectural support for programming languages and operating systems, pages 85--96, New York, NY, USA, 2004. ACM Press.
[5]
M. Dalton, H. Kannan, and C. Kozyrakis. "Raksha: A Flexible Information Flow Architecture for Software Security," In 34th Intl. Symposium on Computer Architecture (ISCA), June 2007.
[6]
M. Tiwari, H. Wassel, B. Mazloom, S. Mysore, F. Chong, and T. Sherwood. "Complete information flow tracking from the gates up," In Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2009.
[7]
M. Tiwari, X. Li, H. M. G. Wassel, F. T. Chong, and T. Sherwood. "Execution Leases: A Hardware-Supported Mechanism for Enforcing Strong Non-Interference," Proceedings of the International Symposium on Microarchitecture (Micro), December 2009. New York, NY

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  • (2024)Automated Assertion Checker Generator and Information Flow Tracking for Security Verification2024 25th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED60706.2024.10528770(1-6)Online publication date: 3-Apr-2024
  • (2024)Enhancing HW-SW Confidentiality Verification for Embedded Processors with SoftFlow’s Advanced Memory Range FeatureVLSI-SoC 2023: Innovations for Trustworthy Artificial Intelligence10.1007/978-3-031-70947-0_13(251-272)Online publication date: 29-Dec-2024
  • (2023)Secure Instruction and Data-Level Information Flow Tracking Model for RISC-VCryptography10.3390/cryptography70400587:4(58)Online publication date: 16-Nov-2023
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    cover image ACM Conferences
    DAC '10: Proceedings of the 47th Design Automation Conference
    June 2010
    1036 pages
    ISBN:9781450300025
    DOI:10.1145/1837274
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 13 June 2010

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    Author Tags

    1. Boolean logic
    2. hardware security
    3. information flow tracking

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    Cited By

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    • (2024)Automated Assertion Checker Generator and Information Flow Tracking for Security Verification2024 25th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED60706.2024.10528770(1-6)Online publication date: 3-Apr-2024
    • (2024)Enhancing HW-SW Confidentiality Verification for Embedded Processors with SoftFlow’s Advanced Memory Range FeatureVLSI-SoC 2023: Innovations for Trustworthy Artificial Intelligence10.1007/978-3-031-70947-0_13(251-272)Online publication date: 29-Dec-2024
    • (2023)Secure Instruction and Data-Level Information Flow Tracking Model for RISC-VCryptography10.3390/cryptography70400587:4(58)Online publication date: 16-Nov-2023
    • (2023)SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC57769.2023.10321922(1-6)Online publication date: 16-Oct-2023
    • (2023)SeVNoC: Security Validation of System-on-Chip Designs With NoC FabricsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.317930742:2(672-682)Online publication date: Feb-2023
    • (2022)RTL-ConTest: Concolic Testing on RTL for Detecting Security VulnerabilitiesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.306656041:3(466-477)Online publication date: Mar-2022
    • (2021)Hardware Information Flow TrackingACM Computing Surveys10.1145/344786754:4(1-39)Online publication date: 3-May-2021
    • (2021)Seeds of SEED: Building and Verifying Foundationally Isolated Hardware Architectures2021 International Symposium on Secure and Private Execution Environment Design (SEED)10.1109/SEED51797.2021.00032(210-214)Online publication date: Sep-2021
    • (2019)HardfailsProceedings of the 28th USENIX Conference on Security Symposium10.5555/3361338.3361354(213-230)Online publication date: 14-Aug-2019
    • (2018)HyperFlowProceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security10.1145/3243734.3243743(1583-1600)Online publication date: 15-Oct-2018
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