skip to main content
10.1145/1837274.1837371acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
research-article

Representative path selection for post-silicon timing prediction under variability

Published: 13 June 2010 Publication History

Abstract

The identification of speedpaths is required for post-silicon (PS) timing validation, and it is currently becoming time-consuming due to manufacturing variations. In this paper we propose a method to find a small set of representative paths that can help monitor a large pool of target paths which are more prone to fail the timing at PS stage, to reduce with the validation effort. We first introduce the concept of effective rank to select a small set of representative paths to predict the target paths with high accuracy. To handle the large dimension and degree of independent random parameter variations, we then allow modeling target path delays using segment delays and formulate it as a convex problem. The identification of segments can be incorporated in design of custom test structures to monitor PS circuit timing behavior. Simulations show that we can use the actual timing information of less than 100 paths or segments to accurately predict up to 3,500 target paths (statistically-critical ones) with more than 1,000 process variables.

References

[1]
Bastani, P., and et. al. Speedpath prediction based on learning from a small set of examples. In DAC (2008).
[2]
Blaauw, D., and et. al. Statistical timing analysis: From basic principles to state of the art. TCAD 27, 4 (2008).
[3]
Callegari, N., and et. al. Path selection for monitoring unexpected systematic timing effects. In ASPDAC (2009).
[4]
Chua, D., and et. al. Network kriging. JSAC 24, 12 (2006).
[5]
Golub, G., and Loan, C. Matrix Computations, 2nd ed. The Johns Hopkins University Press, London, 1989.
[6]
Josephson, D. The good, the bad, and the ugly of silicon debug. In DAC (2006).
[7]
Liu, Q., and Sapatnekr, S. Synthesizing a representative critical path for post-silicon delay prediction. In ISPD (2009).
[8]
Nocedal, J., and Wright, S. Numerical Optimization, 2nd ed. The Springer Press, New York, 2006.
[9]
Turlach, B., and et. al. Simultaneous variable selection. Technometrics 27 (2005).
[10]
Wang, X., and et. al. Path-RO: a novel on-chip critical path delay measurement under process variations. In ICCAD (2008).
[11]
Xie, L., and Davoodi, A. Bound-based identification of timing-violating paths under variability. In ASPDAC (2009).

Cited By

View all
  • (2022)Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to PostsiliconIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309582441:6(1929-1942)Online publication date: Jun-2022
  • (2020)On-Chip Health Monitoring Based on DE-Cluster in 2.5D ICsBio-inspired Computing: Theories and Applications10.1007/978-981-15-3425-6_40(517-526)Online publication date: 2-Apr-2020
  • (2019)EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process VariationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.281871338:4(705-718)Online publication date: Apr-2019
  • Show More Cited By

Index Terms

  1. Representative path selection for post-silicon timing prediction under variability

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    DAC '10: Proceedings of the 47th Design Automation Conference
    June 2010
    1036 pages
    ISBN:9781450300025
    DOI:10.1145/1837274
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 13 June 2010

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. post-silicon validation
    2. process variations

    Qualifiers

    • Research-article

    Funding Sources

    Conference

    DAC '10
    Sponsor:

    Acceptance Rates

    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

    Upcoming Conference

    DAC '25
    62nd ACM/IEEE Design Automation Conference
    June 22 - 26, 2025
    San Francisco , CA , USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)4
    • Downloads (Last 6 weeks)2
    Reflects downloads up to 18 Feb 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2022)Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to PostsiliconIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309582441:6(1929-1942)Online publication date: Jun-2022
    • (2020)On-Chip Health Monitoring Based on DE-Cluster in 2.5D ICsBio-inspired Computing: Theories and Applications10.1007/978-981-15-3425-6_40(517-526)Online publication date: 2-Apr-2020
    • (2019)EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process VariationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.281871338:4(705-718)Online publication date: Apr-2019
    • (2018)Bayesian theory based switching probability calculation method of critical timing path for on-chip timing slack monitoring2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8342036(361-366)Online publication date: Mar-2018
    • (2017)Synthesis of All-Digital Delay Lines2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)10.1109/ASYNC.2017.10(75-82)Online publication date: May-2017
    • (2015)Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path SelectionACM Transactions on Design Automation of Electronic Systems10.1145/274623720:3(1-23)Online publication date: 24-Jun-2015
    • (2015)Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.240155234:5(713-725)Online publication date: May-2015
    • (2014)A Survey on Low-Power Techniques for Single and Multicore SystemsProceedings of the 3rd International Conference on Context-Aware Systems and Applications10.5555/2762722.2762735(69-74)Online publication date: 7-Oct-2014
    • (2014)Identification of testable representative paths for low-cost verification of circuit performance during manufacturing and in-field tests2014 IEEE 32nd VLSI Test Symposium (VTS)10.1109/VTS.2014.6818782(1-6)Online publication date: Apr-2014
    • (2014)Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance MonitorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.228274222:10(2117-2130)Online publication date: Oct-2014
    • Show More Cited By

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media