research-article

Fortifying analog models with equivalence checking and coverage analysis

Authors:

Metha Jeeradit,

James MaoAuthors Info & Claims

DAC '10: Proceedings of the 47th Design Automation Conference

Pages 425 - 430

https://doi.org/10.1145/1837274.1837381

Published: 13 June 2010 Publication History

Abstract

As analog and digital circuits have become more intertwined, we need to create a validation approach that handles both circuit types gracefully. This paper proposes a model-first approach, where one creates functional models of the analog blocks that will work in a HDL simulator, and then uses these models in the same way as HDL models are used for other standard cells: they are used in the full system validation, and the underlying implementations are validated to ensure they meet this specification. While creating functional models for the analog blocks might seem difficult, almost all analog blocks can be modeled as linear systems and we use this property to help create the required functional model.

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Cited By

Chakraborty ASanyal SDasgupta PHazra AMorrison SSurendran SBalasubramanian L(2022)Tracking Coverage Artefacts for Periodic Signals using Sequence-based Abstractions2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID)10.1109/VLSID2022.2022.00036(132-137)Online publication date: Feb-2022
https://doi.org/10.1109/VLSID2022.2022.00036
Sanyal SDasgupta PHazra ADas SMorrison SSurendran SBalasubramanian L(2022)The CoveRT Approach for Coverage Management in Analog and Mixed-Signal Integrated CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.315768641:12(5695-5708)Online publication date: Dec-2022
https://doi.org/10.1109/TCAD.2022.3157686
Sanyal SHazra ADasgupta PMorrison SSurendran SBalasubramanian L(2020)CoveRT: A Coverage Reporting Tool for Analog Mixed-Signal Designs2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID)10.1109/VLSID49098.2020.00038(119-124)Online publication date: Jan-2020
https://doi.org/10.1109/VLSID49098.2020.00038
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Index Terms

Fortifying analog models with equivalence checking and coverage analysis
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design

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Published In

cover image ACM Conferences

DAC '10: Proceedings of the 47th Design Automation Conference

June 2010

1036 pages

ISBN:9781450300025

DOI:10.1145/1837274

General Chair:
Sachin Sapatnekar
Univ. of Minnesota, Minneapolis, MN

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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Association for Computing Machinery

New York, NY, United States

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Published: 13 June 2010

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DAC '10: The 47th Annual Design Automation Conference 2010

June 13 - 18, 2010

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Chakraborty ASanyal SDasgupta PHazra AMorrison SSurendran SBalasubramanian L(2022)Tracking Coverage Artefacts for Periodic Signals using Sequence-based Abstractions2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID)10.1109/VLSID2022.2022.00036(132-137)Online publication date: Feb-2022
https://doi.org/10.1109/VLSID2022.2022.00036
Sanyal SDasgupta PHazra ADas SMorrison SSurendran SBalasubramanian L(2022)The CoveRT Approach for Coverage Management in Analog and Mixed-Signal Integrated CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.315768641:12(5695-5708)Online publication date: Dec-2022
https://doi.org/10.1109/TCAD.2022.3157686
Sanyal SHazra ADasgupta PMorrison SSurendran SBalasubramanian L(2020)CoveRT: A Coverage Reporting Tool for Analog Mixed-Signal Designs2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID)10.1109/VLSID49098.2020.00038(119-124)Online publication date: Jan-2020
https://doi.org/10.1109/VLSID49098.2020.00038
Sanyal SHazra ADasgupta PMorrison SSurendran SBalasubramanian L(2020)The Notion of Cross Coverage in AMS Design Verification2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC47756.2020.9045131(217-222)Online publication date: Jan-2020
https://doi.org/10.1109/ASP-DAC47756.2020.9045131
Tarraf AHedrich L(2019)Automatic Modeling of Transistor Level Circuits by Hybrid Systems with Parameter Variable Matrices2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)10.1109/SMACD.2019.8795271(133-136)Online publication date: Jul-2019
https://doi.org/10.1109/SMACD.2019.8795271
Dubikhin VMyers CSokolov DSyranidis IYakovlev A(2017)Advances in Formal Methods for the Design of Analog/Mixed-Signal SystemsProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3072945(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3072945
Furtig AGlaser GGrimm CHedrich LHeinen SLee HNitsche GOlbrich MRadojicic CSpeicher F(2017)Novel metrics for Analog Mixed-Signal coverage2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)10.1109/DDECS.2017.7934589(97-102)Online publication date: Apr-2017
https://doi.org/10.1109/DDECS.2017.7934589
Ain ASanyal SDasgupta P(2017)A Framework for Automated Feature Based Mixed-Signal Equivalence CheckingVLSI Design and Test10.1007/978-981-10-7470-7_73(779-791)Online publication date: 21-Dec-2017
https://doi.org/10.1007/978-981-10-7470-7_73
Fürtig ASteinhorst SHedrich L(2017)Feature-Based State Space Coverage Metric for Analog Circuit VerificationLanguages, Design Methods, and Tools for Electronic System Design10.1007/978-3-319-62920-9_5(83-101)Online publication date: 11-Nov-2017
https://doi.org/10.1007/978-3-319-62920-9_5
Fürtig AHedrich L(2017)Formal Techniques for Verification and Coverage Analysis of Analog SystemsFormal System Verification10.1007/978-3-319-57685-5_1(1-35)Online publication date: 22-Jun-2017
https://doi.org/10.1007/978-3-319-57685-5_1
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