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Stacking SRAM banks for ultra low power standby mode operation

Published: 13 June 2010 Publication History

Abstract

On-chip SRAM caches have come to dominate the total chip area and leakage power consumed in state-of-the-art microprocessor designs. Such large memories are necessary to attain high performance, however it is critical to minimize the idle currents drawn while these SRAM banks are inactive. This work proposes a novel voltage reduction technique to reduce SRAM leakage power during the standby mode. The design employs an implicit voltage reduction method that "stacks" SRAM banks in series while these blocks are inactive. No explicit DC/DC converters are required to achieve the reduced voltages, which leads to large area reductions over techniques requiring on-chip regulation circuits. This stacking technique reduces the voltage on each block close to the absolute data retention voltage (DRV) of each cell, and achieves a maximum leakage power reduction of 93% from the active power mode. Simulation results show the stability of the scheme around corners, process variations, and on-chip noise.

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Cited By

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  • (2024)Voltage Stacking: A First-Order Modelization of an m × n Asynchronous Array for Chip and Architectural Design ExplorationJournal of Low Power Electronics and Applications10.3390/jlpea1403004414:3(44)Online publication date: 27-Aug-2024
  • (2021)Leakage Reuse for Energy Efficient Near-Memory Computing of Heterogeneous DNN AcceleratorsIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2021.312168711:4(762-775)Online publication date: Dec-2021
  • (2020)Analysis and Design of 4-to-1 Capacitor-Stacking Balancer for Stacked Voltage DomainIEEE Access10.1109/ACCESS.2020.30015988(110252-110263)Online publication date: 2020
  • Show More Cited By

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    cover image ACM Conferences
    DAC '10: Proceedings of the 47th Design Automation Conference
    June 2010
    1036 pages
    ISBN:9781450300025
    DOI:10.1145/1837274
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 13 June 2010

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    Author Tags

    1. low-power memory
    2. stacked SRAM

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    View all
    • (2024)Voltage Stacking: A First-Order Modelization of an m × n Asynchronous Array for Chip and Architectural Design ExplorationJournal of Low Power Electronics and Applications10.3390/jlpea1403004414:3(44)Online publication date: 27-Aug-2024
    • (2021)Leakage Reuse for Energy Efficient Near-Memory Computing of Heterogeneous DNN AcceleratorsIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2021.312168711:4(762-775)Online publication date: Dec-2021
    • (2020)Analysis and Design of 4-to-1 Capacitor-Stacking Balancer for Stacked Voltage DomainIEEE Access10.1109/ACCESS.2020.30015988(110252-110263)Online publication date: 2020
    • (2018)Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme2018 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2018.8350944(1-4)Online publication date: May-2018
    • (2017)Logic Design Partitioning for Stacked Power DomainsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.272958725:11(3045-3056)Online publication date: Nov-2017
    • (2017)A Low-Power Microcontroller in a 40-nm CMOS Using Charge RecyclingIEEE Journal of Solid-State Circuits10.1109/JSSC.2016.263700352:4(950-960)Online publication date: Apr-2017
    • (2017)Floorplan and placement methodology for improved energy reduction in stacked power-domain design2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2017.7858363(444-449)Online publication date: Jan-2017
    • (2016)Lower power by voltage stackingProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898041(1-5)Online publication date: 5-Jun-2016
    • (2016)SRAM voltage stacking2016 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2016.7538879(1634-1637)Online publication date: May-2016
    • (2016)Reliable PUF design using failure patterns from time-controlled power gating2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT.2016.7684085(135-140)Online publication date: Sep-2016
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